US9621113B2ActiveUtilityA1
Pseudo-envelope following power management system
Est. expiryApr 19, 2030(~3.8 yrs left)· nominal 20-yr term from priority
H03F 1/0244H03F 1/025H03F 2200/555H03F 3/189H03F 2200/451H03F 3/24H03F 1/0238H02M 3/07H03F 3/19H03F 3/21H03F 2200/102H03G 3/004H03F 2200/375
84
PatentIndex Score
4
Cited by
719
References
16
Claims
Abstract
Embodiments disclosed in the detailed description relate to a pseudo-envelope follower power management system used to manage the power delivered to a linear RF power amplifier.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1. A power management system for an RF power amplifier comprising:
a parallel amplifier circuit comprising:
an amplifier in communication with a power amplifier supply voltage; and
a voltage offset loop circuit configured to provide a threshold offset current as a feedback signal; and
a multi-level charge pump buck converter comprising:
a switcher control circuit configured to receive the feedback signal from the voltage offset loop circuit and output a logic level indication; and
a frequency lock loop (FLL) in communication with the switcher control circuit and receiving the logic level indication.
2. The power management system of claim 1 , further comprising a coupling circuit coupled to an output of the parallel amplifier circuit, and wherein the feedback signal estimates a magnitude of an offset voltage appearing across the coupling circuit.
3. The power management system of claim 1 , wherein the voltage offset loop circuit comprises a first subtractor circuit, the first subtractor circuit comprising a voltage offset output, the first subtractor circuit configured to receive the power amplifier supply voltage and an output from the parallel amplifier circuit.
4. The power management system of claim 3 , wherein the voltage offset loop circuit comprises a second subtractor circuit, the second subtractor circuit comprising an input coupled to the voltage offset output and an offset error output.
5. The power management system of claim 4 , wherein the voltage offset loop circuit comprises an integrator coupled to the offset error output and wherein the integrator comprises a threshold offset current output.
6. The power management system of claim 1 wherein as the threshold offset current rises above zero current, an output frequency of the multi-level charge pump buck converter is lowered.
7. The power management system of claim 6 , further comprising a power inductor coupled to an output of the multi-level charge pump buck converter, wherein as the output frequency decreases, current output from the power inductor decreases.
8. The power management system of claim 7 , wherein as the current output from the power inductor decreases, an offset voltage within the voltage offset loop circuit decreases.
9. The power management system of claim 1 wherein as the threshold offset current sinks below zero current, an output frequency of the multi-level charge pump buck converter is increased.
10. The power management system of claim 9 , further comprising a power inductor coupled to an output of the multi-level charge pump buck converter, wherein as the output frequency increases, current output from the power inductor increases.
11. The power management system of claim 10 , wherein as the current output from the power inductor increases, an offset voltage within the voltage offset loop circuit increases.
12. A method of controlling a power management system for an RF power amplifier, comprising:
providing a threshold offset current as a feedback signal from a voltage offset loop circuit;
receiving the feedback signal at a switcher control circuit of a multi-level charge pump buck converter;
outputting a logic level indication from the switcher control circuit;
receiving the logic level indication at a frequency lock loop (FLL).
13. The method of claim 12 further comprising estimating, with the feedback signal, a magnitude of an offset voltage appearing across a coupling circuit.
14. The method of claim 12 , further comprising generating a threshold offset current output with an integrator in the voltage offset loop circuit.
15. The method of claim 12 , further comprising lowering an output frequency of the multi-level charge pump buck converter as the threshold offset current rises above zero current.
16. The method of claim 12 , further comprising increasing an output frequency of the multi-level charge pump buck converter as the threshold offset current sinks below zero current.Cited by (0)
No later patents cite this yet.
References (0)
No backward citations on record.