Transistor structure

Abstract

A dynamic random access memory structure is disclosed, in which, the active area is a donut-type pillar at which a novel vertical transistor is disposed and has a gate filled in the central cavity of the pillar and upper and lower sources/drains located in the upper and the lower portions of the pillar respectively. A buried bit line is formed in the substrate beneath the transistor. A word line is horizontally disposed above the gate. A capacitor is disposed above the word line as well as the gate and electrically connected to the upper source/drain through a node contact. The node contact has a reverse-trench shape with the top surface electrically connected to the capacitor and with the bottom of the sidewalls electrically connected to the upper source/drain. The word line passes through the space confined by the reverse-trench shape.

1. A transistor structure comprising:
 a substrate in a shape of donut-type pillar, wherein the donut-type pillar has a toroid shape; 
 a gate dielectric layer covering an inner wall of the donut-type pillar; 
 a gate filled in a central cavity of the donut-type pillar and separated from the inner wall of the donut-type pillar by the gate dielectric layer; 
 a spacer covering an outer wall and a part of the inner wall of the donut-type pillar and a plane of the substrate inside the donut-type pillar; 
 an upper source/drain disposed in the upper portion of the donut-type pillar; and 
 a lower source/drain disposed in the lower portion of the donut-type pillar. 
 
     
     
       2. The transistor structure of  claim 1 , wherein the lower source/drain is in a donut shape. 
     
     
       3. The transistor structure of  claim 1 , wherein the upper source/drain is in a donut shape.