US8168533B2ActiveUtilityA1

Through-silicon via structure and method for making the same

84
Assignee: KUO CHIEN-LIPriority: Mar 9, 2009Filed: Aug 23, 2011Granted: May 1, 2012
Est. expiryMar 9, 2029(~2.7 yrs left)· nominal 20-yr term from priority
Inventors:Chien-Li Kuo
H10W 72/952H10W 72/923H10W 72/244H10W 72/221H10W 72/90H10W 20/20H10W 20/0249H10W 20/217H10W 72/252H10W 20/023
84
PatentIndex Score
6
Cited by
7
References
11
Claims

Abstract

A through-silicon via structure includes a substrate with a first side and a second side, a through-silicon hole connecting the first side and the second side and filled with a conductive material, a passivation layer disposed on and contacting the first side and covering the through-silicon hole, and a protection ring surrounding but not contacting the through-silicon hole and exposed by the first side and the second side. The protection ring is filled with an insulating material.

Claims

exact text as granted — not AI-modified
1. A method for forming a through-silicon via (TSV) structure, comprising:
 providing a substrate with a first side and a second side opposite to said first side; 
 performing an etching procedure to form a through-silicon hole and a protection trench, so that said protection trench surrounds said through-silicon hole, wherein said through-silicon hole is deeper than said protection trench; 
 filling said protection trench and said through-silicon hole with an insulating material; 
 forming a passivation layer comprising a first conductive material and disposed on said first side and covering said through-silicon hole; 
 thinning said substrate from said second side to expose said insulating material in said through-silicon hole; and 
 replacing said insulating material in said through-silicon hole with a second conductive material to form said through-silicon via structure. 
 
     
     
       2. The method of  claim 1 , further comprising:
 continuing to thin said substrate from said second side to expose said insulating material in said protection trench to form a protection ring. 
 
     
     
       3. The method of  claim 2 , wherein said passivation layer covers said protection ring. 
     
     
       4. The method of  claim 2 , wherein said through-silicon hole does not contact said protection ring. 
     
     
       5. The method of  claim 2 , wherein said second conductive material bulges from said second side. 
     
     
       6. The method of  claim 1 , further comprising:
 forming a pad oxide layer on said substrate; 
 forming a nitride layer on said pad oxide layer; and 
 forming a shallow trench isolation in said substrate. 
 
     
     
       7. The method of  claim 1 , wherein the diameter of said through-silicon hole is larger than the trench width of said protection trench so that said etching procedure results in said through-silicon hole being deeper than said protection ring. 
     
     
       8. The method of  claim 1 , further comprising:
 forming at least one of a barrier layer and a liner in said through-silicon hole. 
 
     
     
       9. The method of  claim 1 , wherein said passivation layer is selected from a group consisting of a gate structure, a metal interconnection and a contact etch stop layer (CESL). 
     
     
       10. The method of  claim 1 , wherein thinning said substrate from said second side is carried out by a chemical mechanical polishing procedure. 
     
     
       11. The method of  claim 1 , between filling said protection trench and said through-silicon hole with said insulating material and thinning said substrate from said second side further comprising:
 performing a semiconductor process selected from a group consisting of a gate process for forming a gate, a source/drain process for forming a source/drain and an interconnect process for forming an interconnect.

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