High voltage interface module

Abstract

The present invention provides a voltage conditioning interface module to condition an electrical signal locally. This module receives the unsafe electrical signal at an input port. This input port is electrically coupled to an external sampling point on an electrical circuit or system under test. A conditioning circuit having both a voltage reducing circuit and a voltage limiting circuit provides a reduced voltage. The voltage limiting circuit is in parallel with the output terminals that output the reduced voltage. This arrangement ensures that when a circuit element within the voltage reducing circuit fails, an unsafe condition does not exist across these terminals.

1. A high voltage conditioning interface module to condition an electrical signal locally, comprising:
 an input port to receive the electrical signal from an external sampling point;  
 a conditioning circuit, wherein the conditioning circuit comprises: 
 a voltage reducing circuit having output terminals to output a reduced voltage to test equipment wherein the test equipment is coupled to the output terminals by a low-voltage circuit pathway; and  
 a voltage limiting circuit in parallel with the output terminals to limit a voltage across the output terminals when a circuit element within the voltage reducing circuit and parallel to the output terminals fails open or short circuits; and  
 
 a first electrical pathway to electrically couple the received electrical signal to the conditioning circuit.  
 
   
   
     2. The voltage conditioning circuit of  claim 1 , wherein the voltage reducing network comprises:
 a first resistance; and  
 a second resistance in series with the first resistance, wherein the output terminals are across the second resistance.  
 
   
   
     3. The voltage conditioning circuit of  claim 2 , wherein the ratio of the second resistance to the sum of the first resistance and the second resistance is about 1/101.01. 
   
   
     4. The voltage conditioning circuit of  claim 1 , wherein the voltage limiting circuit comprises a transorb. 
   
   
     5. The voltage conditioning circuit of  claim 1 , wherein the voltage limiting circuit comprises:
 a first diode aligned such that if a voltage across the output terminals exceeds a breakdown voltage, the output terminals are shunted to a reference point; and  
 a second diode in parallel to the first diode but aligned such that forward current flow in the second diode is opposite that of the first diode.  
 
   
   
     6. The voltage conditioning circuit of  claim 1 , wherein:
 the electrical signal does not exceed about 600 volts; and  
 the reduced voltage does not exceed about 40 volts.  
 
   
   
     7. The voltage conditioning circuit of  claim 1 , wherein the reduced voltage signal is provided to a data acquisition system. 
   
   
     8. The voltage conditioning circuit of  claim 1 , wherein an epoxy package encapsulates the conditioning circuit. 
   
   
     9. The voltage conditioning circuit of  claim 1 , wherein the reduced voltage signal is provided to a test equipment. 
   
   
     10. The voltage conditioning circuit of  claim 1 , wherein a failure in either the first resistance or the second resistance does not result in a reduced voltage exceeding a predetermined safe voltage. 
   
   
     11. A method to locally condition a sampled high voltage signal, comprising:
 locally coupling a first circuit pathway to a sampling point;  
 providing the sampled voltage signal to a voltage divider circuit;  
 dropping the sampled voltage across the voltage divider circuit;  
 sampling a reduced voltage at a reduced voltage output;  
 preventing the reduced voltage at the reduced voltage output from exceeding a predetermined voltage level;  
 coupling the reduced voltage output to a remote test system with a low-voltage circuit pathway; and  
 reading the reduced voltage output with data collection equipment.  
 
   
   
     12. The method of  claim 11 , wherein a ratio of the reduced voltage to the sampled voltage is a constant ratio. 
   
   
     13. The method of  claim 11 , wherein preventing the reduced voltage at the reduced voltage output from exceeding a predetermined voltage level further comprises placing a voltage limiting circuit in parallel with the voltage divider circuit at the reduced voltage output. 
   
   
     14. The method of  claim 11 , further comprising providing the reduced voltage output to a data acquisition system through a second circuit pathway. 
   
   
     15. The method of  claim 11 , wherein the sampling point is within a complex system having a plurality of sampling points coupled to remote data acquisition systems. 
   
   
     16. A voltage conditioning interface module to locally condition an electrical signal sampled within a complex system, comprising:
 an input port to receive the electrical signal from an external sampling point within the complex system;  
 an epoxy package encapsulating a conditioning circuit, wherein the conditioning circuit comprises: 
 a voltage divider circuit having a first resistance and a second resistance, wherein output terminals are across the second resistance to provide a reduced voltage output; and  
 a voltage limiting circuit in parallel with the output terminals to limit the reduced voltage across the output terminals when either the first resistance or the second resistance fails;  
 
 a first electrical pathway to electrically couple the received electrical signal to the conditioning circuit; and  
 a low voltage circuit pathway is operable to couple the output terminals to a remote data collection equipment.  
 
   
   
     17. The voltage conditioning circuit of  claim 16 , wherein the voltage limiting circuit comprises a transorb. 
   
   
     18. The voltage conditioning circuit of  claim 16 , wherein the voltage limiting circuit comprises:
 a first diode aligned such that if the reduced voltage across the output terminals exceeds a breakdown voltage, the output terminals are shunted to a reference point; and  
 a second diode in parallel to the first diode but aligned such that forward current flow in the second diode is opposite that of the first diode.  
 
   
   
     19. The voltage conditioning circuit of  claim 16 , wherein the ratio of the second resistance to the sum of the first resistance and the second resistance is about 1/101.01. 
   
   
     20. The voltage conditioning circuit of  claim 16 , wherein:
 the electrical signal does not exceed about 600 volts; and  
 the reduced voltage does not exceed about 40 volts.  
 
   
   
     21. The voltage conditioning circuit of  claim 16 , wherein the reduced voltage is provided to a data acquisition system. 
   
   
     22. The voltage conditioning circuit of  claim 16 , wherein a failure in either the first resistance or the second resistance does not result in a reduced voltage exceeding a predetermined safe voltage, and wherein the failure comprises an open circuit or short circuit.