Interface for microprocessors and network facilities

Abstract

A network facility includes an interface device coupled between a processor member and a network device which has an integrated circuit coupled between an antenna and the interface device. The interface device has a chip selecting member coupled to the integrated circuit for accessing to the integrated circuit, and a reading and a writing control members coupled to the integrated circuit for reading and writing between the integrated circuit and the processor member. The interface device may have a waiting or a reset or an interrupting member coupled to the integrated circuit.

I claim:  
     
       1. A network facility comprising: 
       a processor unit including a data bus and an address bus,  
       an interface device including a data unit and an address unit coupled to said data bus and said address bus of said processor unit respectively, and  
       a network device including an antenna, and an integrated circuit coupled to said antenna and coupled to said interface device,  
       said interface device including a chip selecting unit coupled to said integrated circuit of said network device, for accessing to said integrated circuit of said network device, and for allowing said processor unit to send chip selecting signals to said integrated circuit of said network device,  
       said interface device including a writing control unit coupled to said integrated circuit of said network device, for allowing said integrated circuit of said network device to send out signals to said processor unit via said interface device, and  
       said interface device including a reading control unit coupled to said integrated circuit of said network device, for allowing said processor unit to send out signals to said integrated circuit of said network device via said interface device.  
     
     
       2. The interface device according to  claim 1 , wherein said interface device further includes a waiting unit coupled to said integrated circuit of said network device, for sending waiting control signals to said processor unit, and for controlling said processor unit in a waiting state, when data or information communication between said integrated circuit of said network device and said processor unit is busy. 
     
     
       3. The interface device according to  claim 1 , wherein said interface device further includes a reset unit coupled to said integrated circuit of said network device, for sending resetting signals to said processor unit, and for allowing said processor unit to send chip selecting signals to said integrated circuit of said network device again. 
     
     
       4. The interface device according to  claim 1 , wherein said interface device further includes an interrupting unit coupled to said integrated circuit of said network device, for sending interrupting signals to said processor unit, and for interrupting said processor unit.