Method for achieving low capacitance diffusion pattern filling

Abstract

An automated method for selectively locating fill pattern diffusion regions on a semiconductor substrate. In one embodiment, the present invention determines the locations of active diffusion regions on a semiconductor substrate. The present invention also determines the locations of interconnect lines on the semiconductor substrate. Next, the present invention creates a union of the location of the active diffusion regions on the semiconductor substrate and the location of the interconnect lines on the semiconductor substrate. The present invention uses this union to define allowable locations for placement of fill pattern diffusion regions on the semiconductor substrate such that the fill pattern diffusion regions are not disposed under the interconnect lines.

I claim: 
     
       1. An automated method for selectively locating fill pattern diffusion regions on a semiconductor substrate, the method comprising the steps of: a) determining the location of active diffusion regions on a semiconductor substrate;   b) determining the location of interconnect lines on said semiconductor substrate;   c) creating a union of said location of said active diffusion regions on said semiconductor substrate and said location of said interconnect lines on said semiconductor substrate; and   d) utilizing said union created in step c) to define allowable locations for placement of fill pattern diffusion regions on said semiconductor substrate such that said fill pattern diffusion regions are not disposed under said interconnect lines said fill pattern diffusion regions adapted to provide a more consistent diffusion pattern density and said fill pattern diffusion regions adapted to enhance planarity in subsequent planarization processes.   
     
     
       2. The automated method for selectively locating fill pattern diffusion regions on a semiconductor substrate as recited in claim 1 wherein step a) further comprises the steps of: a1) determining the location of active diffusion regions of a first conductivity type on said semiconductor substrate; and   a2) determining the location of active diffusion regions of a second conductivity type on said semiconductor substrate.   
     
     
       3. The automated method for selectively locating fill pattern diffusion regions on a semiconductor substrate as recited in claim 1 wherein step c) further comprises: creating said union by logically ORing said location of said active diffusion regions on said semiconductor substrate and said location of said interconnect lines on said semiconductor substrate.   
     
     
       4. The automated method for selectively locating fill pattern diffusion regions on a semiconductor substrate as recited in claim 1 wherein step d) further comprises: utilizing said union created in step c) in an automated pattern generator to define said allowable locations for placement of said fill pattern diffusion regions on said semiconductor substrate such that said fill pattern diffusion regions are not disposed, by said automated pattern generator, under said interconnect lines.   
     
     
       5. A method for generating a diffusion pattern mask which selectively locates fill pattern diffusion regions on a semiconductor substrate, the diffusion pattern mask generation method comprising the steps of: a) determining the location of active diffusion regions on a semiconductor substrate;   b) determining the location of interconnect lines on said semiconductor substrate;   c) creating a union of said location of said active diffusion regions on said semiconductor substrate and said location of said interconnect lines on said semiconductor substrate;   d) utilizing said union created in step c) to determine allowable locations for placement of fill pattern diffusion regions on said semiconductor substrate such that said fill pattern diffusion regions are not disposed under said interconnect lines; and   e) using said union created in step c) and said allowable locations determined in step d) to generate a diffusion mask layer wherein said diffusion mask layer locates said active diffusion regions, said interconnect lines, and said fill pattern diffusion regions on said semiconductor substrate such that said fill pattern diffusion regions do not underlie said interconnect lines said fill pattern diffusion regions adapted to provide a more consistent diffusion pattern density and said fill pattern diffusion regions adapted to enhance planarity in subsequent planarization processes.   
     
     
       6. The method for generating a diffusion pattern mask as recited in claim 5 wherein step a) further comprises the steps of: a1) determining the location of active diffusion regions of a first conductivity type on said semiconductor substrate; and   a2) determining the location of active diffusion regions of a second conductivity type on said semiconductor substrate.   
     
     
       7. T he method for generating a diffusion pattern mask as recited in claim 5 wherein step c) further comprises the steps of: creating said union by logically ORing said location of said active diffusion regions on said semiconductor substrate and said location of said interconnect lines on said semiconductor substrate.   
     
     
       8. The method for generating a diffusion pattern mask as recited in claim 5 wherein step d) further comprises the steps of: utilizing said union created in step c) in an automated pattern generator to define said allowable locations for placement of said fill pattern diffusion regions on said semiconductor substrate such that said fill pattern diffusion regions are not disposed, by said automated pattern generator, under said interconnect lines.