Apparatus for externally timing high voltage cycles of non-volatile memory system

Abstract

An apparatus which allows the pulse duration of the high voltage pulses used in the programming and erase operations of a non-volatile memory system to be determined by an external timing signal instead of the internal timer normally used. Control of the pulse duration by the internal timer is disabled by gating the timer output signal with the external signal in a manner such that the gate output signal (which triggers the end of the high voltage pulse) is only generated when the external timing signal has a predetermined value. By controlling the value of the external timing signal, the pulse duration can be varied and have values other than those which would result from use of the internal timer.

I claim: 
     
       1. A memory system comprising: an array of memory cells;   a high voltage pulse generator for producing a high voltage pulse to program or erase a memory cell contained in the array, wherein the high voltage pulse generator further comprises: means for initiating the high voltage pulse in response to a first control signal; and   timer means for producing a second control signal for terminating the high voltage pulse after a first predetermined period of time; and     means for disabling production of the second control signal by the timer means and for producing a third control signal after a second predetermined period of time, the third control signal acting to terminate the high voltage pulse.   
     
     
       2. The memory system of claim 1, wherein the means for disabling production of the second control signal by the timer means and for producing a third control signal further comprises: means for generating an external timing control signal having a first and a second value, wherein the first value disables production of the second control signal by the timer means and the second value enables production of the third control signal which terminates the high voltage pulse.   
     
     
       3. The memory system of claim 2, wherein the means for generating the external timing control signal generates the first value of the external timing control signal in response to a first code signal provided by a user of the memory system. 
     
     
       4. The memory system of claim 3, wherein the means for generating the external timing control signal generates the second value of the external timing control signal in response to a second code signal provided by a user of the memory system, the second code signal being provided after the second predetermined period of time. 
     
     
       5. The memory system of claim 4, wherein the first and second code signals have the same value. 
     
     
       6. The memory system of claim 2, further comprising: control means for controlling operation of the memory system in response to memory program and memory erase commands, the memory program and erase commands initiating a plurality of memory program and erase sub-operations which include producing the high voltage pulse to program or erase a memory cell contained in the array; and   flow control means for bypassing one of the plurality of memory program and erase sub-operations not involved in producing the high voltage pulse.   
     
     
       7. The memory system of claim 6, wherein the flow control means bypasses the program or erase sub-operations in response to control parameters stored in a data storage element of the memory system. 
     
     
       8. The memory system of claim 6, further comprising: means for generating the control parameters for bypassing the program or erase sub-operation in response to generation of the first value of the external timing control signal.   
     
     
       9. A method for externally determining the duration of a high voltage pulse for programming or erasing a memory cell contained in a memory system, the programming or erasing of the memory cell requiring a plurality of program and erase sub-operations which include producing the high voltage pulse, the pulse duration being determined by an internal timer contained in the memory system, the method comprising: initiating a high voltage pulse;   providing a first external signal which disables control of the high voltage pulse duration by the internal timer; and   providing a second external signal after a predetermined period of time which acts to terminate the high voltage pulse.   
     
     
       10. The method of claim 9, further comprising: causing the memory system to bypass one of the plurality of memory program and erase sub-operations not involved in producing the high voltage pulse.   
     
     
       11. The method of claim 9, wherein the first and second external signals are separated by said predetermined period of time. 
     
     
       12. The method of claim 10, wherein the memory system is caused to bypass one of the plurality of the memory program and erase sub-operations not involved in producing the high voltage pulse in response to the first external signal. 
     
     
       13. A memory system comprising: an array of memory cells;   a high voltage pulse generator for producing a high voltage pulse to program or erase a memory cell contained in the array, wherein the high voltage pulse generator further comprises: a high voltage pulse initiator for initiating the high voltage pulse in response to a first control signal; and   a timer for producing a second control signal for terminating the high voltage pulse after a first predetermined period of time; and     a control signal disabler for disabling production of the second control signal by the timer means and for producing a third control signal after a second predetermined period of time, the third control signal acting to terminate the high voltage pulse.   
     
     
       14. The memory system of claim 13, wherein the control signal disabler further comprises: an external timing control signal generator for generating an external timing control signal having a first and a second value, wherein the first value disables production of the second control signal by the timer and the second value enables production of the third control signal which terminates the high voltage pulse.   
     
     
       15. The memory system of claim 14, wherein the external timing control signal generator generates the first value of the external timing control signal in response to a first code signal provided by a user of the memory system. 
     
     
       16. The memory system of claim 15, wherein the external timing control signal generator generates the second value of the external timing control signal in response to a second code signal provided by a user of the memory system, the second code signal being provided after the second predetermined period of time. 
     
     
       17. The memory system of claim 16, wherein the first and second code signals have the same value. 
     
     
       18. The memory system of claim 14, further comprising: control means for controlling operation of the memory system in response to memory program and memory erase commands, the memory program and erase commands initiating a plurality of memory program and erase sub-operations which include producing the high voltage pulse to program or erase a memory cell contained in the array; and   flow control means for bypassing one of the plurality of memory program and erase sub-operations not involved in producing the high voltage pulse.   
     
     
       19. The memory system of claim 18, wherein the flow control means bypasses the program or erase sub-operations in response to control parameters stored in a data storage element of the memory system. 
     
     
       20. The memory system of claim 19, further comprising: a control parameter generator for generating the control parameters in response to generation of the first value of the external timing control signal.   
     
     
       21. A memory system comprising an array of memory cells;   control means for controlling operation of the memory system by initiating an operation performed on a memory cell contained in the array of memory cells, the duration of the operation being determined by a timer internal to the memory system; and   an external timing module which disables the timer internal to the memory system and enables a timer external to the memory system which determines the duration of the operation.   
     
     
       22. The memory system of claim 21, wherein the external timing module disables the timer internal to the memory system in response to a first control signal initiated by a user. 
     
     
       23. The memory system of claim 22, wherein the external timing module enables the timer external to the memory system in response to a second control signal initiated by a user. 
     
     
       24. The memory system of claim 23, wherein the control means initiates the operation performed on the memory cell in response to the second control signal. 
     
     
       25. The memory system of claim 24, wherein the timer external to the memory system terminates the operation performed on the memory cell by generating a third control signal after a predetermined period of time. 
     
     
       26. The memory system of claim 21, wherein the operation performed on the memory cell includes a plurality of memory program and erase sub-operations, the memory system further comprising: flow control means for bypassing one of the plurality of memory program and erase sub-operations.   
     
     
       27. The memory system of claim 26, wherein the flow control means bypasses the program or erase sub-operation in response to control parameters stored in a data storage element of the memory system.