Transistor circuits including fringeless transistors and method of making the same

Abstract

A first field effect transistor includes a first active region and a first gate electrode that includes a first semiconductor gate electrode portion and a first metallic gate electrode portion. The first active region includes a first source region and a first drain region that are laterally spaced from each other by a first channel along a first channel direction. The first gate electrode laterally extends along a first gate electrode direction that is perpendicular to the first channel direction. A maximum lateral extent of the first metallic gate electrode portion along the first gate electrode direction is greater than a maximum lateral extent of the first semiconductor gate electrode portion along the first gate electrode direction.

What is claimed is: 
     
         1 . A semiconductor structure comprising a first field effect transistor, wherein the first field effect transistor comprises a first active region and a first gate electrode that includes a first semiconductor gate electrode portion and a first metallic gate electrode portion, wherein:
 the first active region comprises a first source region and a first drain region that are laterally spaced from each other by a first channel along a first channel direction;   the first gate electrode laterally extends along a first gate electrode direction that is perpendicular to the first channel direction; and   a maximum lateral extent of the first metallic gate electrode portion along the first gate electrode direction is greater than a maximum lateral extent of the first semiconductor gate electrode portion along the first gate electrode direction.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein a first end wall of the first metallic gate electrode portion that is parallel to the first channel direction and is vertically coincident with a first end wall of the first semiconductor gate electrode portion. 
     
     
         3 . The semiconductor structure of  claim 2 , wherein a straight line segment of a periphery of a top surface of the first active region is contained entirely within a vertical plane including the first end wall of the first metallic gate electrode portion and the first end wall of the first semiconductor gate electrode portion. 
     
     
         4 . The semiconductor structure of  claim 2 , wherein the first semiconductor gate electrode portion has a same lateral extent along the first gate electrode direction as a lateral extent of the first active region along the first gate electrode direction. 
     
     
         5 . The semiconductor structure of  claim 4 , wherein the first metallic gate electrode portion further comprises:
 a second end wall that is parallel to the first channel direction and is vertically coincident with a second end wall of the first semiconductor gate electrode portion; and   a third end wall that is parallel to the first channel direction and is located entirely outside an area of the first active region in a plan view along a vertical direction.   
     
     
         6 . The semiconductor structure of  claim 5 , wherein:
 the first end wall and the second end wall has a first channel direction dimension along the first channel direction; and   the third end wall has a second channel direction dimension along the first channel direction, wherein the second channel direction dimension is greater than the first channel direction dimension.   
     
     
         7 . The semiconductor structure of  claim 1 , wherein:
 the first semiconductor gate electrode portion has a uniform lateral dimension along the first channel direction, the uniform lateral dimension being a first channel direction dimension; and   the first metallic gate electrode portion comprises a first portion having the first channel direction dimension along the first channel direction and a second portion having a second channel direction dimension that is greater than the first channel direction dimension.   
     
     
         8 . The semiconductor structure of  claim 7 , wherein:
 the first metallic gate electrode portion has a metallic gate electrode thickness between a topmost surface and a bottommost surface; and   the second portion of the first metallic gate electrode portion has a lesser thickness than the metallic gate electrode thickness.   
     
     
         9 . The semiconductor structure of  claim 7 , wherein the first portion of the first metallic gate electrode portion comprises:
 a first segment having a vertical extent of the metallic gate electrode thickness; and   a second segment underlying the second portion and having a vertical extent that is less than the metallic gate electrode thickness.   
     
     
         10 . The semiconductor structure of  claim 7 , wherein the second portion of the first metallic gate electrode portion has an areal overlap with the first active region in a plan view along a vertical direction. 
     
     
         11 . The semiconductor structure of  claim 7 , wherein:
 the first portion of the first metallic gate electrode portion has a lateral extent along the first gate electrode direction that is the same as a lateral extent of the first active region along the first gate electrode direction; and   the second portion of the first metallic gate electrode portion comprises a first area having an areal overlap with the first active region in a plan view and a second area that does not have any areal overlap with the first active region.   
     
     
         12 . The semiconductor structure of  claim 1 , wherein the first metallic gate electrode portion comprises:
 a first portion having a first thickness and located entirely within an area of the first active region in a plan view; and   a second portion having a second thickness that is less than the first thickness.   
     
     
         13 . The semiconductor structure of  claim 12 , wherein the second portion of the first metallic gate electrode portion comprises:
 a pair of first segments overlying the first active region and laterally spaced apart from each other along the first channel direction by the first portion of the first metallic gate electrode portion; and   a second segment located outside an area of the first active region in a plan view and adjoined to the first portion and the pair of first segments.   
     
     
         14 . The semiconductor structure of  claim 1 , further comprising a second field effect transistor comprising a second active region and a second gate electrode that comprises a second semiconductor gate electrode portion and a second metallic gate electrode portion, wherein:
 the second active region comprises a second source region and a second drain region that are laterally spaced from each other by a second channel along a second channel direction;   the second gate electrode laterally extends along a second gate electrode direction that is perpendicular to the second channel direction; and   a maximum lateral extent of the second metallic gate electrode portion along the second gate electrode direction is the same as a maximum lateral extent of the second semiconductor gate electrode portion along the second gate electrode direction.   
     
     
         15 . A method of forming a semiconductor structure, comprising:
 forming a first trench isolation structure around a first portion of a semiconductor substrate;   forming a first patterned stack including a first gate dielectric, a first semiconductor gate electrode portion, and a first hardmask gate cap over the first portion of a semiconductor substrate;   forming a first source region and a first drain region within a remaining segment of the first portion of the semiconductor substrate, whereby a first active region is formed;   forming a planarization dielectric layer over the first trench isolation structure and the first active region such that a top surface of the planarization dielectric layer is coplanar with a top surface of the first hardmask gate cap;   forming a recess region around the first patterned stack by vertically recessing a portion of the planarization dielectric layer;   forming a stepped cavity by removing the first hardmask gate cap, wherein the stepped cavity comprises a volume from which the first hardmask gate cap is removed and a volume of the peripheral recess region; and   forming a first metallic gate electrode portion in the stepped cavity.   
     
     
         16 . The method of  claim 15 , wherein the first metallic gate electrode portion comprises a first portion having a first thickness and a second portion having a second thickness that is less than the first thickness. 
     
     
         17 . The method of  claim 15 , wherein the recess region comprises:
 a first area having an areal overlap with the first active region; and   a second area that does not have any areal overlap with the first active region.   
     
     
         18 . The method of  claim 15 , further comprising forming a first dielectric gate spacer around the first patterned stack prior to formation of the first source region and the first drain region, wherein the portion of the planarization dielectric layer is vertically recessed by performing an anisotropic etch process that collaterally recesses a portion of the first dielectric gate spacer. 
     
     
         19 . The method of  claim 15 , further comprising vertically recessing the first trench isolation structure such that a recessed top surface of the first trench isolation structure is formed below a horizontal plane including a bottom surface of the first hardmask gate cap. 
     
     
         20 . The method of  claim 15 , further comprising:
 forming a first layer stack including a first gate dielectric layer, a first gate semiconductor material portions, and a first hardmask plate over the first portion of the semiconductor substrate;   forming a first shallow isolation trench around the first portion of the semiconductor substrate, wherein:   the first trench isolation structure is formed in the first shallow isolation trench and around the first patterned stack; and   the first patterned stack is formed by patterning the first layer stack, wherein the first hardmask gate cap comprises a patterned portion of the first hardmask plate, the first semiconductor gate electrode portion comprises a patterned portion of the first gate semiconductor material portions, and the first gate dielectric comprises a patterned portion of the first gate dielectric layer.