Methods for Programming and Accessing Resistive Change Elements Using Neutral Voltage Conditions

Abstract

The present disclosure generally relates to circuit architectures for programming and accessing resistive change elements. The circuit architectures can program and access resistive change elements using neutral voltage conditions. The present disclosure also relates to methods for programming and accessing resistive change elements using neutral voltage conditions. The present disclosure additionally relates to sense amplifiers configurable into initializing configurations for initializing the sense amplifiers and comparing configurations for comparing voltages received by the sense amplifiers. The sense amplifiers can be included in the circuit architectures of the present disclosure.

What is claimed is: 
     
         1 . A method for programming at least one resistive change element in a resistive change element array, said method comprising:
 providing neutral voltage conditions for a plurality of resistive change elements in a resistive change element array, wherein multiple resistive change elements of said plurality of resistive change elements are in electrical communication with a plurality of even bit lines and a plurality of word lines, wherein plural resistive change elements of said plurality of resistive change elements are in electrical communication with a plurality of odd bit lines and said plurality of word lines, wherein said plurality of even bit lines and a plurality of global bit lines are in electrical communication with a plurality of first selection devices, and wherein said plurality of odd bit lines and said plurality of global bit lines are in electrical communication with a plurality of second selection devices;   biasing said plurality of global bit lines;   selecting at least one resistive change element from said plurality of resistive change elements;   electrically connecting said plurality of global bit lines to one of said plurality of even bit lines and said plurality of odd bit lines;   applying an electrical stimulus to each of said at least one resistive change element;   restoring neutral voltage conditions for resistive change elements impacted by said applying an electrical stimulus to each of said at least one resistive change element step; and   biasing global bit lines impacted by said applying an electrical stimulus to each of said at least one resistive change element step.   
     
     
         2 . The method of  claim 1 , wherein said providing neutral voltage conditions for a plurality of resistive change elements in a resistive change element array step is concurrent with said biasing said plurality of global bit lines step. 
     
     
         3 . The method of  claim 1 , wherein said providing neutral voltage conditions for a plurality of resistive change elements in a resistive change element array step comprises:
 floating said plurality of even bit lines;   floating said plurality of odd bit lines; and   applying a voltage for providing neutral voltage conditions to said plurality of word lines.   
     
     
         4 . The method of  claim 1 , wherein said biasing said plurality of global bit lines step comprises:
 floating said plurality of global bit lines; and   applying a voltage for providing neutral voltage conditions to said plurality of global bit lines.   
     
     
         5 . The method of  claim 1 , wherein each resistive change element in said plurality of resistive change elements is adjustable between a high resistive state and a low resistive state and wherein a resistance of said low resistive state is less than a resistance of said high resistive state. 
     
     
         6 . The method of  claim 5 , wherein said electrical stimulus is for adjusting a resistive state of a resistive change element to said high resistive state. 
     
     
         7 . The method of  claim 5 , wherein said electrical stimulus is for adjusting a resistive state of a resistive change element to said low resistive state. 
     
     
         8 . The method of  claim 1 , wherein said plurality of first selection devices are field effect transistors and said plurality of second selection devices are field effect transistors. 
     
     
         9 . A method for accessing at least one resistive change element in a resistive change element array, said method comprising:
 providing neutral voltage conditions for a plurality of resistive change elements in a resistive change element array, wherein multiple resistive change elements of said plurality of resistive change elements are in electrical communication with a plurality of even bit lines and a plurality of word lines, wherein plural resistive change elements of said plurality of resistive change elements are in electrical communication with a plurality of odd bit lines and said plurality of word lines, wherein said plurality of even bit lines and a plurality of global bit lines are in electrical communication with a plurality of first selection devices, and wherein said plurality of odd bit lines and said plurality of global bit lines are in electrical communication with a plurality of second selection devices;   biasing said plurality of global bit lines;   selecting at least one resistive change element from said plurality of resistive change elements;   electrically connecting said plurality of global bit lines to one of said plurality of even bit lines and said plurality of odd bit lines;   generating a voltage indicative of a resistive state for each of said at least one resistive change element;   determining a resistive state for each of said at least one resistive change element based on said voltage indicative of a resistive state for that resistive change element and a voltage for determining a resistive state;   restoring neutral voltage conditions for resistive change elements impacted by said generating a voltage indicative of a resistive state for each of said at least one resistive change element step; and   biasing global bit lines impacted by said generating a voltage indicative of a resistive state for each of said at least one resistive change element step.   
     
     
         10 . The method of  claim 9 , wherein said providing neutral voltage conditions for a plurality of resistive change elements in a resistive change element array step is concurrent with said biasing said plurality of global bit lines step. 
     
     
         11 . The method of  claim 9 , wherein said providing neutral voltage conditions for a plurality of resistive change elements in a resistive change element array step comprises:
 floating said plurality of even bit lines;   floating said plurality of odd bit lines; and   applying a voltage for providing neutral voltage conditions to said plurality of word lines.   
     
     
         12 . The method of  claim 9 , wherein said biasing said plurality of global bit lines step comprises:
 floating said plurality of global bit lines; and   applying a voltage for providing neutral voltage conditions to said plurality of global bit lines.   
     
     
         13 . The method of  claim 9 , wherein said plurality of first selection devices are field effect transistors and said plurality of second selection devices are field effect transistors. 
     
     
         14 . The method of  claim 9 , wherein said generating a voltage indicative of a resistive state for each of said at least one resistive change element step comprises:
 applying a voltage for accessing said at least one resistive change element to each word line in electrical communication with a resistive change element of said at least one resistive change element; and   sinking an amount of current for accessing a resistive change element of said at least one resistive change element from each global bit line in electrical communication with a resistive change element of said at least one resistive change element.   
     
     
         15 . The method of  claim 14 , wherein said amount of current for accessing a resistive change element of said at least one resistive change element is an amount of current for a read operation. 
     
     
         16 . The method of  claim 14 , wherein said amount of current for accessing a resistive change element of said at least one resistive change element is an amount of current for a set verify operation. 
     
     
         17 . The method of  claim 14 , wherein said amount of current for accessing a resistive change element of said at least one resistive change element is an amount of current for a reset verify operation. 
     
     
         18 . The method of  claim 9 , further comprising applying said voltage for determining said resistive state to a reference line of said resistive change element array prior to determining a resistive state for each of said at least one resistive change element based on said voltage indicative of a resistive state for that resistive change element and a voltage for determining a resistive state step. 
     
     
         19 . The method of  claim 18 , wherein said electrically connecting said plurality of global bit lines to one of said plurality of even bit lines and said plurality of odd bit lines step is concurrent with said applying said voltage for determining said resistive state to a reference line of said resistive change element array step.