Semiconductor device

Abstract

A semiconductor device includes a plurality of active patterns protruding from a substrate, a gate structure intersecting the plurality of active patterns, a plurality of source/drain regions respectively on the plurality of active patterns at opposite sides of the gate structure, and source/drain contacts intersecting the plurality of active patterns, each of the source/drain contacts connected in common to the source/drain regions thereunder, each of the plurality of source/drain regions including a first portion in contact with a top surface of the active pattern thereunder, the first portion having a width substantially increasing as a distance from the substrate increases, and a second portion extending from the first portion, the second portion having a width substantially decreasing as a distance from the substrate increases, bottom surfaces of the source/drain contacts being lower than an interface between the first and second portions.

1 . A semiconductor device, comprising:
 a plurality of active patterns protruding from a substrate;   a gate structure intersecting the plurality of active patterns;   a plurality of source/drain regions respectively on the plurality of active patterns at opposite sides of the gate structure; and   source/drain contacts intersecting the plurality of active patterns, each of the source/drain contacts connected in common to the source/drain regions thereunder,   wherein each of the plurality of source/drain regions includes:
 a first portion in contact with a top surface of the active pattern thereunder, the first portion having a width substantially increasing as a distance from the substrate increases, and 
 a second portion extending from the first portion, the second portion having a width substantially decreasing as a distance from the substrate increases, and 
   wherein bottom surfaces of the source/drain contacts are lower than an interface between the first and second portions.   
     
     
         2 . The semiconductor device as claimed in  claim 1 , wherein the bottom surfaces of the source/drain contacts are higher than the top surfaces of the plurality of the active patterns. 
     
     
         3 . The semiconductor device as claimed in  claim 1 , wherein the bottom surfaces of the source/drain contacts are flat surfaces substantially parallel to a top surface of the substrate. 
     
     
         4 . The semiconductor device as claimed in  claim 1 , wherein the bottom surfaces of the source/drain contacts include uneven and curved surfaces. 
     
     
         5 . (canceled) 
     
     
         6 . The semiconductor device as claimed in  claim 1 , wherein each of the source/drain regions further comprises a third portion at a lower level than the top surfaces of the plurality of active patterns, the third portion being in contact with sidewalls of the active pattern under each of the source/drain regions,
 wherein a lowermost end of the third portion is spaced apart from the sidewalls of the active pattern.   
     
     
         7 .- 8 . (canceled) 
     
     
         9 . The semiconductor device as claimed in  claim 1 , further comprising a device isolation pattern on the substrate to partially cover sidewalls of the plurality of active patterns, the device isolation pattern including:
 a first region under the gate structure, and   second regions at opposite sides of the gate structure, at least one of the second regions including a plurality of recess regions having bottom surfaces lower than a top surface of the first region.   
     
     
         10 . The semiconductor device as claimed in  claim 9 , wherein the plurality of recess regions includes:
 first recess regions among the plurality of active patterns; and   second recess regions at opposite sides of the plurality of active patterns, bottom surfaces of the first recess regions being higher than bottom surfaces of the second recess regions.   
     
     
         11 . (canceled) 
     
     
         12 . The semiconductor device as claimed in  claim 10 , wherein the first recess regions include an air gap. 
     
     
         13 . The semiconductor device as claimed in  claim 12 , wherein at least one of the source/drain contacts includes an extension extending into the air gap. 
     
     
         14 . The semiconductor device as claimed in  claim 12 , further comprising a contact etch stop layer covering inner surfaces of the first and second recess regions and extending onto the plurality of source/drain regions and sidewalls of the gate structure, the air gap being defined by the contact etch stop layer. 
     
     
         15 . The semiconductor device as claimed in  claim 1 , wherein the gate structure includes:
 a gate electrode intersecting the plurality of active patterns; and   a gate dielectric pattern between the gate electrode and the plurality of active patterns, the gate dielectric pattern including:
 a first sub-gate dielectric pattern, and 
 a second sub-gate dielectric pattern having a higher a dielectric constant than that of the first sub-gate dielectric pattern. 
   
     
     
         16 . A semiconductor device, comprising:
 a substrate including a first region and a second region different from each other;   a plurality of first active patterns protruding from the substrate of the first region, the first active patterns being spaced apart from each other at equal distances;   a plurality of second active patterns protruding from the substrate of the second region, the second active patterns being spaced apart from each other at different distances;   a first gate structure intersecting the plurality of first active patterns;   a second gate structure intersecting the plurality of second active patterns;   a plurality of first source/drain regions respectively on the plurality of first active patterns at one side of the first gate structure;   a plurality of second source/drain regions respectively on the plurality of second active patterns at one side of the second gate structure;   a first source/drain contact intersecting the plurality of first active patterns, the first source/drain contact being connected in common to the plurality of first source/drain regions; and   a second source/drain contact intersecting the plurality of second active patterns, the second source/drain contact being connected in common to the plurality of second source/drain regions,   wherein a top surface of the first source/drain contact is lower than a top surface of the second source/drain contact.   
     
     
         17 .- 23 . (canceled) 
     
     
         24 . The semiconductor device as claimed in  claim 16 , wherein each of the plurality of first source/drain regions includes:
 a first portion in contact with a top surface of the first active pattern thereunder, the first portion having a width substantially increasing as a distance from the substrate increases; and   a second portion extending from the first portion, the second portion having a width substantially decreasing as a distance from the substrate increases,   wherein a bottom surface of the first source/drain contact is lower than an interface between the first and second portions.   
     
     
         25 .- 28 . (canceled) 
     
     
         29 . The semiconductor device as claimed in  claim 16 , wherein the plurality of second active patterns include:
 a pair of first sub-active patterns spaced apart from each other by a first distance; and   a second sub-active pattern spaced apart from one of the pair of first sub-active patterns by a second distance greater than the first distance,   wherein the plurality of second source/drain regions include first, second, and third sub-source/drain regions on the pair of first sub-active patterns and the second sub-active pattern, respectively, and   wherein a conductivity type of the first and second sub-source/drain regions is different from that of the third sub-source/drain region.   
     
     
         30 . The semiconductor device as claimed in  claim 29 , wherein the second source/drain contact includes an extension extending between the second sub-active pattern and the first sub-active pattern adjacent to the second sub-active pattern. 
     
     
         31 . A semiconductor device, comprising:
 a plurality of active patterns protruding from a substrate;   a gate structure intersecting the plurality of active patterns;   a plurality of source/drain regions respectively on the plurality of active patterns at opposite sides of the gate structure; and   source/drain contacts intersecting the plurality of active patterns, each of the source/drain contacts being connected in common to the source/drain regions thereunder,   wherein each of the plurality of source/drain regions includes at least one sidewalls with a triangular profile, the triangular profile having a sharp edge extending away from a sidewall of a corresponding source/drain contact, and   wherein distances between a bottom of the substrate and corresponding lowermost surfaces of the source/drain contacts are smaller than respective distances of the bottom of the substrate and corresponding sharp edges.   
     
     
         32 . The semiconductor device as claimed in  claim 31 , wherein each of the plurality of source/drain regions includes:
 a first portion in contact with a top surface of the active pattern thereunder, the first portion having a width substantially increasing as a distance from the bottom of the substrate increases; and   a second portion extending from the first portion, the second portion having a width substantially decreasing as a distance from the bottom of the substrate increases,   wherein the sharp edges of the triangular profiles are at an interface between the first and second portions.   
     
     
         33 . The semiconductor device as claimed in  claim 31 , further comprising air gaps among the plurality of source/drain regions, each source/drain contact being on at least one corresponding air gap. 
     
     
         34 . The semiconductor device as claimed in  claim 31 , wherein at least one of bottom surfaces of the source/drain contacts has a different profile than other source/drain contacts. 
     
     
         35 . The semiconductor device as claimed in  claim 34 , wherein the at least one of the bottom surfaces of the source/drain contacts having a different profile has a larger contact area with a corresponding source/drain region thereunder.