Clocking for pipelined routing

Abstract

An integrated circuit may have pipelined programmable interconnects that are configured to select between a routing signal stored in a register and the identical routing signal bypassing the register. The pipelined programmable interconnect may send the selected routing signal over a wire to the next pipelined programmable interconnect circuitry. The integrated circuit may also have clock routing circuitry to select respective clock signals for the registers in the different pipelined programmable interconnects. The clock routing circuitry may include first interconnects that convey region clocks, second interconnects that conveys routing clocks, a first selector circuit to select routing clocks among the region clocks, and a second selector circuit to select routing clocks for the respective registers.

What is claimed is: 
     
         1 . An integrated circuit, comprising:
 a first clock selection stage that selects from a first plurality of clock signals and that outputs a second plurality of clock signals;   a second clock selection stage that selects from the second plurality of clock signals that and that outputs a third plurality of clock signals; and   pipelined routing resources that receive the third plurality of clock signals.   
     
     
         2 . The integrated circuit of  claim 1 , wherein the first clock selection stage comprises a first number of multiplexers, and wherein the second clock selection stage comprises a second number of multiplexers. 
     
     
         3 . The integrated circuit of  claim 1 , wherein the first number of multiplexers is at most equal to the number of clock signals in the first plurality of clock signals. 
     
     
         4 . The integrated circuit of  claim 1 , wherein each multiplexer in the second clock selection stage has a number of inputs that is at most equal to the number of clock signals in the first plurality of clock signals. 
     
     
         5 . The integrated circuit of  claim 1 , wherein each multiplexer in the second clock selection stage has a number of inputs that is less than the number of clock signals in the second plurality of clock signals. 
     
     
         6 . The integrated circuit of  claim 1 , wherein all of the multiplexers in the second clock selection stage have the same number of inputs. 
     
     
         7 . The integrated circuit of  claim 1 , wherein at least two of the multiplexers in the second clock selection stage have a different number of inputs. 
     
     
         8 . The integrated circuit of  claim 1 , further comprising:
 an additional pipelined routing resource that directly receives one of the second plurality of clock signals without passing through the second clock selection stage.   
     
     
         9 . The integrated circuit of  claim 1 , wherein the pipelined routing resources are operable in a pipeline mode and a non-pipeline mode. 
     
     
         10 . A method of operating an integrated circuit, comprising:
 generating a plurality of region clocks;   with a first clock selection stage, receiving the plurality of region clocks and outputting a plurality of routing clocks;   with a second clock selection stage, receiving the plurality of routing clocks and outputting a plurality of selected clock signals; and   receiving the plurality of selected clock signals at a plurality of pipelined routing resources.   
     
     
         11 . The method of  claim 10 , selectively placing a pipelined routing resource in the plurality of pipelined routing resources in a pipeline mode. 
     
     
         12 . The method of  claim 11 , selectively placing the pipelined routing resource in a non-pipeline mode. 
     
     
         13 . The method of  claim 10 , further comprising:
 directly receiving one of the plurality of routing clock signals at an additional pipelined routing resource.   
     
     
         14 . The method of  claim 10 , further comprising:
 with a first multiplexer in the second clock selection stage, selecting among a first number of routing clock signals; and   with a second multiplexer in the second clock selection stage, selecting among a second number of routing clock signals that is different than the first number.   
     
     
         15 . An integrated circuit, comprising:
 a first functional block that includes a first group of pipelined routing resources;   a second functional block that includes a second group of pipelined routing resources; and   routing paths connecting the first functional block to the second functional block, wherein at least two pipelined routing resources in the first group receive a different number of clock signals.   
     
     
         16 . The integrated circuit of  claim 15 , wherein at least two pipelined routing resources in the second group receive a different number of clock signals. 
     
     
         17 . The integrated circuit of  claim 15 , wherein each pipelined routing resource in the first and second groups of pipelined routing resources comprises a register that can be selectively bypassed. 
     
     
         18 . The integrated circuit of  claim 15 , wherein the routing paths are arranged in a staggered routing arrangement. 
     
     
         19 . The integrated circuit of  claim 15 , wherein a first pipelined routing resource in the first group receives a first number of clock signals, wherein a second pipelined routing resource in the second group receives a second number of clock signals that is different than the first number, and wherein the first pipelined routing resource is directly connected to the second pipelined routing resource via one of the routing paths. 
     
     
         20 . The integrated circuit of  claim 19 , wherein a third pipelined routing resource in the second group receives the first number of clock signals, and wherein the first pipelined routing resource is also directly connected to the third pipelined routing resource.