Replacement metal gate including dielectric gate material

Abstract

A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.

What is claimed is: 
     
         1 . A method of fabricating a semiconductor device, the method comprising:
 forming at least one semiconductor fin on a semiconductor substrate;   forming an etch stop layer on an upper surface of the at least one semiconductor fin;   forming a plurality of gate formation layers on the etch stop layer and the substrate, the plurality of gate formation layers including a dummy gate layer formed from a dielectric material;   patterning the plurality of gate formation layers to form a plurality of dummy gate elements on the etch stop layer, each dummy gate element formed from a material selected from a group comprising of boron carbide (BC), carbon (C), silicon dioxide (SiO 2 ), and a silicon boron carbide material that contains nitrogen (SiB:C(N));   depositing a spacer layer that conforms with an outer surface of each dummy gate element;   etching the spacer layer to form a spacer on each sidewall of the dummy gate elements and etching a portion of the etch stop layer located between each dummy gate element to expose a portion of the semiconductor fin;   depositing a contact dielectric layer that fills a void between the spacers, and covers an outer surface of the spacers and an upper portion of the dummy gate elements;   performing a planarization process selective to one of boron carbide (BC), carbon (C), silicon dioxide (SiO 2 ), and a silicon boron carbide material that contains nitrogen (SiB:C(N)) such that dummy gate element is used as an etch stop layer so as form an upper surface of the contact dielectric layer flush with an upper surface of each spacer and an upper surface of each dummy gate element;   removing the dummy gate elements to form respective trenches between a pair of respective spacers;   depositing at least one work function metal layer in the trenches to conform against sidewalls of each spacer; and   filling each trench with a metal gate material to form a respective metal gate element such that the upper surface of the metal gate element is flush with the at least one work function metal layer, each spacer, and the contact dielectric layer.