Semiconductor device and method for manufacturing same

Abstract

According to one embodiment, a semiconductor device, includes: a first semiconductor region of a first conductivity type; a second semiconductor region provided on the first semiconductor region, an impurity concentration of the second semiconductor region being lower than an impurity concentration of the first semiconductor region; a third semiconductor region of a second conductivity type provided on the second semiconductor region; and a fourth semiconductor region provided on the third semiconductor region or in a portion of the third semiconductor region. A lattice strain of the fourth semiconductor region is greater than a lattice strain of the third semiconductor region.

1 . (canceled) 
     
     
         2 . A semiconductor device, comprising:
 a first electrode;   a first semiconductor region of a first conductivity type, the first semiconductor region being provided on the first electrode and electrically connected with the first electrode;   a second semiconductor region provided on the first semiconductor region, an impurity concentration of the second semiconductor region being lower than an impurity concentration of the first semiconductor region, the second semiconductor region including a first pat region and a second part region, the second part region being arranged with the first part region in a first direction crossing a second direction from the first electrode toward the first semiconductor region;   a third semiconductor region of a second conductivity type provided on the first part region, the third semiconductor region including a third part region and a fourth part region, the fourth part region being arranged with the third part region in a third direction crossing the second direction, the fourth part region being located between the third part region and the second part region;   a fourth semiconductor region of the first conductivity type, the fourth semiconductor region being provided on the third part region,   a fifth semiconductor region provided on the fourth part region, a lattice strain of the fifth semiconductor region being greater than a lattice strain of the third part region, and greater than a lattice strain of the fourth part region;   a second electrode provided on the second part region;   an insulating film provided between the second electrode and the second part region.   
     
     
         3 . The device according to  claim 2 , wherein the fifth semiconductor region includes an impurity different from an impurity included in the third semiconductor region. 
     
     
         4 . The device according to  claim 3 , wherein the impurity included in the fifth semiconductor region includes an inert element. 
     
     
         5 . The device according to  claim 4 , wherein the impurity is at least one selected from Ar, Si, and C. 
     
     
         6 . The device according to  claim 2 , wherein an impurity concentration of the fifth semiconductor region is higher than an impurity concentration of the third semiconductor region. 
     
     
         7 . The device according to  claim 2 , wherein the first semiconductor region, the second semiconductor region, the third semiconductor region, the fourth semiconductor region and the fifth semiconductor region include silicon carbide. 
     
     
         8 . The device according to  claim 2 , wherein
 the first semiconductor region is a substrate having a first surface and including hexagonal silicon carbide, and   the first surface of the substrate is tilted more than 0 degrees and not more than 8 degrees with respect to a basal plane of the silicon carbide.   
     
     
         9 . The device according to  claim 8 , wherein the substrate includes 4H-SiC. 
     
     
         10 . The device according to  claim 2 , wherein the fourth semiconductor region includes an impurity different from an impurity included in the third semiconductor region. 
     
     
         11 . The device according to  claim 10 , wherein the impurity included in the fourth semiconductor region includes an inert element. 
     
     
         12 . The device according to  claim 11 , wherein the impurity is at least one selected from Ar, Si, and C. 
     
     
         13 . The device according to  claim 2 , wherein an impurity concentration of the fourth semiconductor region is higher than an impurity concentration of the third semiconductor region. 
     
     
         14 . The device according to  claim 2 , wherein
 the impurity concentration of the second semiconductor region is not less than 8×10 14  cm −3  and not more than 1×10 17  cm −3 ,   an impurity concentration of the third semiconductor region is not less than 1×10 16  cm −3  and not more than 5×10 19  cm −3 , and   an impurity concentration of the fourth semiconductor region is not less than 5×10 17  cm −3  and not more than 1×10 21  cm −3 .   
     
     
         15 . The device according to  claim 2 , wherein the first semiconductor region, the second semiconductor region, the third semiconductor region, and the fourth semiconductor region include silicon carbide. 
     
     
         16 . The device according to  claim 2 , wherein
 the first semiconductor region is a substrate having a first surface and including hexagonal silicon carbide, and   the first surface of the substrate is tilted more than 0 degrees and not more than 8 degrees with respect to a basal plane of the silicon carbide.   
     
     
         17 . The device according to  claim 16 , wherein the substrate includes 4H-SiC.