Memory controller

Abstract

A memory controller includes an digitally programmable delay unit having a selectable delay time receiving a read-enable signal and outputting a delayed read-enable signal. The delay time is selected in response to an externally applied delay-control signal. A sampling unit in the memory controller outputs data received from a separate memory, in synchronization with the delayed enable signal. The delay time may be a multiple of the period of a clock signal.

What is claimed is: 
     
         1 . A memory controller comprising:
 a programmable delay unit configured to receive a periodic read-enable signal and to output a delayed periodic read-enable signal having a variable delay time selected in response to a delay-control signal; and   a sampling unit configured to output, in synchronization with the delayed periodic read-enable signal, data read out from a memory coupled to the memory controller,   wherein the programmable delay unit generates a plurality of delay signals having different delay times by repeatedly delaying the received read-enable signal based on edges of a clock signal, and selectively outputs one of the delay signals as the delayed read-enable signal.   
     
     
         2 . The memory controller of  claim 1 , wherein each of the plurality of delay signals is synchronized with the clock signal. 
     
     
         3 . The memory controller of  claim 1 , wherein the delay-control signal is a digital signal controlling the delay time of the programmable delay unit and is supplied by a user. 
     
     
         4 . The memory controller of  claim 1 , wherein the delay-control signal controls the delay time to approximately equal to an access time of the memory controller. 
     
     
         5 . The memory controller of  claim 1 , wherein the sampling unit comprises a latch circuit that receives the delayed read-enable signal and data and outputs the data signal, in synchronization with the delayed read-enable signal. 
     
     
         6 . The memory controller of  claim 1 , wherein the memory controller is formed on a first integrated circuit and the memory is formed on a separated second integrated circuit. 
     
     
         7 . A memory controller, comprising:
 a programmable delay unit configured to receive a periodic read-enable signal and to output a delayed periodic read-enable signal having a variable delay time selected in response to a delay-control signal,   wherein the programmable delay unit comprises:   a multi-tap delay block receiving the read-enable signal, and outputting a plurality of delay signals having different delay times by repeatedly delaying the received read-enable signal based on a clock signal; and   a switch unit configured to select one of the plurality of delay signals and to output the selected delay signal as the delayed read-enable signal, in response to the delay-control signal.   
     
     
         8 . The memory controller of  claim 7 , wherein the multi-tap delay block comprises a plurality of delay cells, each of which delays an input signal based on edges of the clock signal and outputs the delayed signal. 
     
     
         9 . The memory controller of  claim 8 , wherein each of the delay cells is formed of a flip-flop. 
     
     
         10 . The memory controller of  claim 7 , wherein the multi-tap delay block comprises a plurality n of delay cells in which an output terminal of a k-th delay cell is connected to an input terminal of a (k+1)th delay cell, wherein n is a natural number, wherein k is a natural number that is not less than 1 and not greater than n−1,
 wherein the first one of the plurality n of delay cells receives the read-enable signal, delays the received read-enable signal based on edges of the clock signal, and outputs a delayed read-enable signal in synchronization with the clock signal. 
 
     
     
         11 . The memory controller of  claim 10 , wherein the k-th delay cell is formed of a positive edge-triggered flip-flop,
 wherein the (k+1)th delay cell is formed of a negative edge-triggered flip-flop.   
     
     
         12 . The memory controller of  claim 10 , wherein the multi-tap delay block further comprises a plurality m of delay cells in which an output terminal of a i-th delay cell is connected to an input terminal of a (i+1)th delay cell, wherein m is a natural number, wherein i is a natural number that is not less than 1 and not greater than m−1,
 wherein the first one of the plurality m of delay cells receives the read-enable signal, 
 wherein each of the plurality n of delay cells is formed of a positive edge-triggered flip-flop, 
 wherein each of the plurality m of delay cells is formed of a negative edge-triggered flip-flop. 
 
     
     
         13 . The memory controller of  claim 7 , wherein the switch unit comprises:
 a delay selector configured to output a switching control signal that controls the delay time according to the delay-control signal; and   a switching device configured to select and output one of the delay signals in response to the switching control signal.   
     
     
         14 . The memory controller of  claim 13 , wherein the switching device is a multiplexer.