Integrated circuit device comprises an interface to transmit a first code, a strobe signal after a delay and data to a dynamic random access memory (dram)

Abstract

An integrated circuit device comprises an interface to transmit a first code, a strobe signal after a delay and data to a dynamic random access memory (DRAM). The first code indicates that data is to be written to the DRAM. The first code is registered by the DRAM on one or more edges of an external clock signal received by the DRAM. The strobe signal specifies one or more discrete points in time synchronous with the external clock signal at which the data is registered by the DRAM.

1 . An integrated circuit device comprising:
 an interface to transmit to a dynamic random access memory (DRAM):
 a first code to indicate that data is to be written to the DRAM, wherein the first code is registered by the DRAM on one or more edges of an external clock signal received by the DRAM; 
 after a delay, a strobe signal specifying one or more discrete points in time synchronous with the external clock signal at which the data is registered by the DRAM; and 
 the data. 
   
     
     
         2 . The integrated circuit device of  claim 1  wherein the data comprises a plurality of bits transmitted consecutively at different times, wherein the plurality of bits are registered by an interface of the DRAM at the one or more discrete points in time and synchronous with the external clock signal. 
     
     
         3 . The integrated circuit device of  claim 2  wherein the interface transmits a second code to the DRAM, the second code to indicate whether the DRAM is to perform a precharge operation after the data is written, wherein the second code is registered by the DRAM on one or more edges of the external clock signal before at least one of the bits of the plurality of bits is registered by the DRAM. 
     
     
         4 . The integrated circuit device of  claim 3  wherein the second code is transmitted to the DRAM before any bit of the plurality of bits is transmitted. 
     
     
         5 . The integrated circuit device of  claim 1  wherein the data is registered by the DRAM at one or more discrete points in time synchronous with the external clock signal. 
     
     
         6 . The integrated circuit device of  claim 1  wherein the interface transmits a terminate signal to the DRAM, wherein the terminate signal indicates when the DRAM is to stop registering the data. 
     
     
         7 . A method of operation of an integrated circuit device for communicating with a dynamic random access memory (DRAM), the method comprising:
 conveying first write command information to the DRAM, wherein the first write command information includes multiple bits to specify a first write operation, wherein the first write command information is registered by the DRAM on one or more edges of an external clock signal;   after a first delay time relative to conveying the first write command information, conveying a first strobe signal, to the DRAM, over a first signal line, wherein the first strobe signal is associated with the first write command information such that the first strobe signal indicates when the DRAM is to begin registering first data associated with the first write operation; and   conveying first data to the DRAM over a set of signal lines that are separate from the first signal line.   
     
     
         8 . The method of  claim 7  further comprising:
 conveying second write command information to the DRAM after the first write command information is conveyed, wherein the second write command information includes multiple bits to specify a second write operation, wherein the second write command information is registered by the DRAM on one or more edges of the external clock signal; 
 after a second delay time relative to conveying the second write command information, conveying a second strobe signal to the DRAM over the first signal line, wherein the second strobe signal is associated with the second write command information such that the second strobe signal indicates when the DRAM is to begin registering second data associated with the second write operation; and 
 conveying second data to the DRAM over the set of signal lines that are separate from the first signal line. 
 
     
     
         9 . The method of  claim 8  wherein the second write command information is conveyed before the first data is conveyed. 
     
     
         10 . The method of  claim 8  wherein the second write command information is conveyed while the first data is conveyed. 
     
     
         11 . The method of  claim 7  further comprising:
 conveying read command information to the DRAM after the first write command information is conveyed, wherein the read command information includes multiple bits to specify a read operation, wherein the read command information is registered by the DRAM on one or more edges of the external clock signal; and 
 receiving read data associated with the read command information from the DRAM over the set of signal lines that are separate from the first signal line. 
 
     
     
         12 . The method of  claim 11  wherein the read command information is conveyed before the first data is conveyed. 
     
     
         13 . The method of  claim 11  wherein the read command information is conveyed while the first data is conveyed. 
     
     
         14 . The method of  claim 11  further comprising:
 after a second delay time relative to conveying the read command information, conveying a second strobe signal to the DRAM over the first signal line, wherein the second strobe signal is associated with the read command information such that the second strobe signal indicates when the DRAM is to begin outputting read data associated with the read operation. 
 
     
     
         15 . The method of  claim 7  further comprising conveying subsequent command information to the DRAM after the first write command information is conveyed, wherein the subsequent command information is registered by the DRAM on one or more edges of the external clock signal. 
     
     
         16 . The method of  claim 15  wherein the subsequent command information is conveyed before the first data is conveyed. 
     
     
         17 . The method of  claim 15  wherein the subsequent command information is conveyed while the first data is conveyed. 
     
     
         18 . The method of  claim 7  wherein conveying the first write command information includes conveying the first write command information in a predetermined phase relationship with respect to the external clock signal. 
     
     
         19 . The method of  claim 7  further comprising conveying a terminate signal to indicate when the DRAM is to end registering first data, wherein the strobe signal is conveyed at a first time and the terminate signal is conveyed at a second time; and
 the method further comprising determining an interval of time that transpires between the first time and the second time based on an amount of data to transfer to the DRAM. 
 
     
     
         20 . The method of  claim 7  wherein first data is conveyed during a plurality of clock cycles of the external clock signal. 
     
     
         21 . The method of  claim 7  further comprising conveying a terminate signal to indicate when the DRAM is to end registering first data, wherein the terminate signal includes information that indicates, after the first write operation, whether to perform a precharge operation. 
     
     
         22 . The method of  claim 7  wherein the first write command information includes a control bit to specify whether to perform a precharge operation after the first write operation. 
     
     
         23 . A method of operation of an integrated circuit device for communicating with a dynamic random access memory (DRAM), the method comprising:
 conveying first write command information to the DRAM, wherein the first write command information specifies a first write operation associated with first data;   after a first delay time relative to conveying the first write command information, conveying a first strobe signal to the DRAM over a first signal line, wherein the first strobe signal is associated with the first write command information such that the first strobe signal indicates when the DRAM is to begin registering first data associated with the first write operation;   conveying second write command information to the DRAM, wherein the second write command information specifies a second write operation;   after a second delay time relative to conveying the second write command information, conveying a second strobe signal to the DRAM over the first signal line, wherein the second strobe signal is associated with the second write command information such that the second strobe signal indicates when the DRAM is to begin registering second data associated with the second write operation; and   conveying first data associated with the first write command information over a set of signal lines that are separate from the first signal line, wherein the second write command information is received by the DRAM before the first data is received by the DRAM.   
     
     
         24 . The method of  claim 23  wherein conveying the first write command information includes conveying the first write command information in a predetermined phase relationship with respect to an external clock signal. 
     
     
         25 . The method of  claim 23  wherein the first write command information includes at least multiple bits to specify the first write operation and at least one control bit to specify, after the first write operation, whether to perform a precharge operation.