Data look ahead to reduce power consumption

Abstract

Portions of a digital signal are buffered prior to being provided to a sub-system (e.g., a segmented DAC of a LDD) that is responsive to the digital signal. While being buffered, there is a determination, based on the buffered portions of the digital signal, of when one or more portions of the sub-system and/or another sub-system can be switched from a first state to a second state, where the second state results in less power dissipation than the first state. Based on results of the determination(s), the state of one or more portions of the sub-system and/or another sub-system is/are selectively switched from the first state to the second state, or vice versa. Eventually, the portions of the digital signal are provided to the sub-system so that the sub-system can respond to the portions of the digital signal.

1 . A system, comprising:
 a driver configured to receive a plurality of digital video signals, wherein the driver includes   a plurality of digital-to-analog converters (DACs), which include a separate DAC for each of the plurality of digital video signals received by the driver;   wherein each of the DACs of the driver includes a corresponding plurality of sub-DACs, with currents output by the sub-DACs of the DAC combined to provide an analog output current that is output by the DAC; and   data look-ahead and control circuitry corresponding to each of the DACs and configured to
 receive one of the digital video signals received by the driver; 
 store portions of the one of the digital video signals prior to providing the portions of the one of the digital video signals to the corresponding DAC; 
 determine, based on the stored portions of the one of the digital video signals, when one or more sub-DACs of the corresponding DAC can be switched from a first state to a second state, where the second state results in less power dissipation than the first state; and 
 selectively switch the state of one or more sub-DACs of the corresponding DAC, when it is determined that one or more sub-DACs of the corresponding DAC can be switched from the first state to the second state. 
   
     
     
         2 . The system of  claim 1 , wherein the data look-ahead and control circuitry corresponding to each of the DACs of the driver includes a multi-register pipeline configured to receive, and configured to store portions of, one of the digital video signals received by the driver, prior to providing the portions of the one of the digital video signals to the corresponding DAC. 
     
     
         3 . The system of  claim 1 , wherein:
 the data look-ahead and control circuitry corresponding to each of the DACs is also configured to
 determine, based on the stored portions of the one of the digital video signals, when one or more sub-DACs of the corresponding DAC should be switched from the second state to the first state; and 
 selectively switch the state of one or more sub-DACs of the corresponding DAC, when it is determined that one or more sub-DACs of the corresponding DAC should be switched from the second state to the first state. 
   
     
     
         4 . The system of  claim 1 , wherein:
 the first state comprises a first power mode; and   the second state comprises a second power mode that results in less power dissipation than the first power mode.   
     
     
         5 . The system of  claim 4 , wherein:
 the first power mode comprises a normal power mode; and   the second power mode comprises a sleep or reduced power mode.   
     
     
         6 . The system of  claim 4 , wherein:
 the first power mode involves providing one or more sub-DACs of the corresponding DAC with a normal bias current; and   the second power mode involves providing one or more sub-DACs of the corresponding DAC with a reduced bias current.   
     
     
         7 . The system of  claim 1 , further comprising:
 a controller configured to perform video processing of the digital video signals before they are provided to the driver.   
     
     
         8 . The system of  claim 1 , further comprising:
 a plurality of light emitting elements, each of which is adapted to be driven in dependence on one of the analog output currents output by one of the DACs.   
     
     
         9 . The system of  claim 8 , wherein:
 the plurality of light emitting elements include
 a red light emitting element; 
 a green light emitting element; and 
 a blue light emitting element; 
   the plurality of digital video signals, that the driver is configured to receive, include
 a first digital video signal in dependence on which the red light emitting element is driven; 
 a second digital video signal in dependence on which the green light emitting element is driven; and 
 a third digital video signal in dependence on which the blue light emitting element is driven; and 
   the plurality of DACs of the driver include
 a first DAC that outputs a first analog output current that drives the red light emitting element; 
 a second DAC that outputs a second analog output current that drives the green light emitting element; and 
 a third DAC that outputs a third analog output current that drives the blue light emitting element. 
   
     
     
         10 . The system of  claim 9 , wherein the data look-ahead and control circuitry corresponding to each of the DACs include:
 first data look-ahead and control circuitry located between a first input of the driver, which receives the first digital video signal, and the first DAC;   second data look-ahead and control circuitry located between a second input of the driver, which receives the second digital video signal, and the second DAC; and   third data look-ahead and control circuitry located between a third input of the driver, which receives the third digital video signal, and the third DAC.   
     
     
         11 . A system, comprising:
 a first digital-to-analog converter (DAC) responsive to a first digital video signal, wherein the first DAC includes a first plurality of sub-DACs; and   first data look-ahead and control circuitry configured to
 receive the first digital video signal and to store portions of the first digital video signal, prior to providing the portions of the first digital video signal to the first DAC; and 
 selectively adjust bias currents provided to at least some of the first plurality of sub-DACs of the first DAC based on the stored portions of the first digital video signal. 
   
     
     
         12 . The system of  claim 11 , wherein the first data look-ahead and control circuitry is configured to reduce bias currents provided to those sub-DACs of the first DAC that are not being used to produce an analog output of the first DAC, and are not going to be used for at least a specified time. 
     
     
         13 . The system of  claim 11 , further comprising:
 a second digital-to-analog converter (DAC) responsive to a second digital video signal, wherein the second DAC includes a second plurality of sub-DACs;   second data look-ahead and control circuitry configured to
 receive the second digital video signal and to store portions of the second digital video signal, prior to providing the portions of the second digital video signal to the second DAC; and 
 selectively reduce bias currents provided to at least some of the second plurality of sub-DACs of the second DAC based on the stored portions of the second digital video signal; and 
   a third digital-to-analog converter (DAC) responsive to a third digital video signal, wherein the third DAC includes a third plurality of sub-DACs;   third data look-ahead and control circuitry configured to
 receive the third digital video signal and to store portions of the third digital video signal, prior to providing the portions of the third digital video signal to the third DAC; and 
 selectively reduce bias currents provided to at least some of the third plurality of sub-DACs of the third DAC based on the stored portions of the third digital video signal. 
   
     
     
         14 . The system of  claim 13 , wherein:
 the first data look-ahead and control circuitry includes a first multi-register pipeline;   the second data look-ahead and control circuitry includes a second multi-register pipeline; and   the third data look-ahead and control circuitry includes a third multi-register pipeline.   
     
     
         15 . The system of  claim 13 , further comprising:
 a first light emitting element driven by an analog output of the first DAC;   a second light emitting element driven by an analog output of the second DAC; and   a third light emitting element driven by an analog output of the third DAC.   
     
     
         16 . The system of  claim 15 , wherein:
 currents output by the first plurality of sub-DACs of the first DAC are combined to provide an analog output of the first DAC;   currents output by the second plurality of sub-DACs of the second DAC are combined to provide an analog output of the second DAC; and   currents output by the third plurality of sub-DACs of the third DAC are combined to provide an analog output of the third DAC.   
     
     
         17 . The system of  claim 16 , wherein:
 the system comprises a projector system; and   wherein the first, second and third DACs and the first, second and third data look-ahead and control circuitry are parts of a driver of the projector system.   
     
     
         18 . The system of  claim 14 , wherein:
 each of the first, second and third data look-ahead and control circuitry includes a corresponding plurality of decoders and logic circuitry.   
     
     
         19 . A system, comprising:
 first, second and third digital-to-analog converters (DACs) responsive, respectively, to first, second and third digital video signals; and   first, second, and third data look-ahead and control circuitry configured to selectively adjust bias currents associated, respectively, with the first, second, and third DACs, based on portions of the first, second and third digital video signals before said portions are provided to the first, second and third DACs.   
     
     
         20 . The system of  claim 19 , wherein the bias currents are selectively reduced to reduce power consumption by the DACs. 
     
     
         21 . The system of  claim 20 , wherein:
 the first data look-ahead and control circuitry is configured to reduce bias currents provided to sub-DACs of the first DAC that are not being used to produce an analog output of the first DAC, and are not going to be used for at least a specified time;   the second data look-ahead and control circuitry is configured to reduce bias currents provided to sub-DACs of the second DAC that are not being used to produce an analog output of the second DAC, and are not going to be used for at least the specified time; and   the third data look-ahead and control circuitry is configured to reduce bias currents provided to sub-DACs of the third DAC that are not being used to produce an analog output of the third DAC, and are not going to be used for at least the specified time.   
     
     
         22 . A method for use with a system including first, second and third digital-to-analog converters (DACs) that are responsive, respectively, to first, second and third digital video signals, the method comprising:
 (a) buffering portions of the first, second and third digital video signals before said portions are provided, respectively, to the first, second and third DACs;   (b) selectively adjusting bias currents associated, respectively, with the first, second, and third DACs, based on the buffered portions of the first, second and third digital video signals before said portions are provided to the first, second and third DACs; and   (c) providing the portions of the first, second and third digital video signals, respectively, to the first, second, and third DACs.   
     
     
         23 . The method of  claim 22 , wherein step (b) includes:
 (b.1) reducing bias currents provided to sub-DACs of the first DAC that are not being used to produce an analog output of the first DAC, and are not going to be used for at least a specified time;   (b.2) reducing bias currents provided to sub-DACs of the second DAC that are not being used to produce an analog output of the second DAC, and are not going to be used for at least the specified time; and   (b.3) reducing bias currents provided to sub-DACs of the third DAC that are not being used to produce an analog output of the third DAC, and are not going to be used for at least the specified time.   
     
     
         24 . The method of  claim 23 , further comprising:
 (d) driving first, second and third light emitting elements, respectively, with the analog outputs of the first, second and third DACs.