Apparatus and methods of nanopatterning and applications of same

Abstract

A method for patterning nanostructures in a semiconductor heterostructure, which has at least a first layer and a second layer, wherein the first layer has a first surface and an opposite, second surface, the second layer has a first surface and an opposite, second surface, and the first layer is deposited over the second layer such that the second surface of the first layer is proximate to the first surface of the second layer. The method includes the steps of making indentations in a pattern on the first surface of the first layer of the semiconductor heterostructure; bonding the semiconductor heterostructure to a support substrate such that the first surface of the first layer of the semiconductor heterostructure is faced to the support substrate; etching off the second layer of the semiconductor heterostructure; and depositing a third layer over the second surface of the first layer of the semiconductor heterostructure.

1 . A method for patterning nanostructures in a semiconductor heterostructure having at least a first layer and a second layer, wherein the first layer has a first surface and an opposite, second surface, the second layer has a first surface and an opposite, second surface, and the first layer is deposited over the second layer such that the second surface of the first layer is proximate to the first surface of the second layer, comprising the steps of:
 (a) making indentations in a pattern on the first surface of the first layer of the semiconductor heterostructure;   (b) bonding the semiconductor heterostructure to a support substrate such that the first surface of the first layer of the semiconductor heterostructure is faced to the support substrate;   (c) etching off the second layer of the semiconductor heterostructure; and   (d) depositing a third layer over the second surface of the first layer of the semiconductor heterostructure to allow nanostructures to grow in a pattern thereon a surface of the third layer which is distant away from the second surface of the first layer.   
     
     
         2 . The method of  claim 1 , wherein the making step comprises the steps of:
 (a) positioning an indenter over the first surface of the first layer of the semiconductor heterostructure at a desired position;   (b) applying a load to the indenter to produce an indentation at the desired position; and   (c) repeating steps (a) and (b) to make indentations in a desired pattern,
 wherein the nanostructures are grown in a pattern corresponding to the indentations in a desired pattern. 
   
     
     
         3 . The method of  claim 2 , wherein the indenter comprises a nanoscale tip capable of producing a desired indention. 
     
     
         4 . The method of  claim 3 , wherein the nanoscale tip has an end profile of one of a circle, square, triangle, rhombus, pyramid, cube corner, polygon and a desired geometric shape. 
     
     
         5 . The method of  claim 2 , wherein the load is less than a threshold value. 
     
     
         6 . The method of  claim 1 , wherein the nanostructures comprise quantum dots, nanowires, nanorods, or nanotubes. 
     
     
         7 . The method of  claim 1 , wherein the first to third layers comprise a GaAs layer, an AlAs layer and an InAs layer, respectively. 
     
     
         8 . The method of  claim 1 , further comprising the steps of
 (a) depositing a fourth layer over the grown nanostructures on the third layer; and   (b) depositing a fifth layer over the fourth layer to allow nanostructures to grow 3-dimensionally therein.   
     
     
         9 . The method of  claim 8 , wherein the fourth and fifth layers comprise a GaAs layer and an InAs layer, respectively. 
     
     
         10 . A semiconductor heterostructure with nanostructures in a pattern formed according to the method of  claim 1 . 
     
     
         11 . An apparatus for patterning nanostructures in a semiconductor heterostructure, comprising:
 (a) a positioning device capable of moving in three dimensions;   (b) an indenter coupled to the position device;   (c) a load device for applying a load to the indenter for producing an indentation on a surface of the semiconductor heterostructure;   (d) a controller in communication with the positioning device for controlling the indenter to move to a desired position over the surface of the semiconductor heterostructure to produce an indentation thereon; and   (e) means for depositing a semiconductor layer over the indented surface of the semiconductor heterostructure as to allow nanostructures to grow from another surface of the semiconductor heterostructure that is opposite to the indented surface.   
     
     
         12 . The apparatus of  claim 11 , wherein the semiconductor heterostructure comprises:
 (a) a GaAs buffer layer having a thickness substantially around 500 nm grown on an epiready Si-doped GaAs(100) wafer;   (b) an AlAs marker layer having a thickness substantially around 100 nm deposited on the GaAs buffer layer; and   (c) a GaAs top layer having a thickness substantially around 300 nm deposited on the AlAs marker layer.   
     
     
         13 . The apparatus of  claim 11 , wherein the indenter comprises a nanoscale tip capable of producing a desired indention, and wherein the nanoscale tip has an end profile of one of a circle, square, triangle, rhombus, pyramid, cube corner, polygon and a desired geometric shape. 
     
     
         14 . A method for patterning nanostructures in a semiconductor, comprising the steps of:
 (a) indenting a surface of the semiconductor to make nano-sized volumes of dislocations thereon in a desired pattern; and   (b) forming a semiconductor layer over the indented surface of the semiconductor to allow nanostructures to grow corresponding to the desired pattern on another surface of the semiconductor that is opposite to the indented surface.   
     
     
         15 . The method of  claim 14 , wherein the indenting step is performed with an indenter. 
     
     
         16 . A semiconductor with nanostructures in a pattern formed according to the method of  claim 14 . 
     
     
         17 . A method for growing nanostructures in a pattern with a semiconductor heterostructure having at least a first layer and a second layer, wherein the first layer has a first surface and an opposite, second surface, the second layer has a first surface and an opposite, second surface, and the first layer is deposited over the second layer such that the second surface of the first layer is proximate to the first surface of the second layer, comprising the steps of:
 (a) making indentations in a pattern on the first surface of the first layer of the semiconductor heterostructure; and   (b) growing nanostructures at a surface that is separated from the first surface of the first layer of the semiconductor heterostructure, wherein each nanostructure grows at a position corresponding to one of the indentations.   
     
     
         18 . The method of  claim 17 , wherein the step of growing nanostructures comprises the steps of (a) bonding a third layer with the first layer; (b) depositing a fourth layer over the third layer; and (c) growing nanostructures at a surface of the fourth layer that is distant away and separated from the first layer. 
     
     
         19 . The method of  claim 18 , wherein the nanostructures as grown form a pattern that is substantially identical to the pattern of the indentations. 
     
     
         20 . The method of  claim 18 , wherein the third and fourth layers comprise a GaAs layer and an InAs layer, respectively, further comprising the steps of
 (a) depositing a fifth layer of GaAs over the grown nanostructures on the fourth layer of InAs; and   (b) depositing a sixth layer of InAs over the fifth layer of GaAs to allow nanostructures to grow therein at positions corresponding to the positions of the nanostructures on the fourth layer of InAs, wherein the fifth layer and sixth layer form a combination of a layer of GaAs and a layer of InAs with nanostructures grown on the layer of InAs.   
     
     
         21 . The method of  claim 20 , further comprising the step of depositing additional a combination of a layer of GaAs and a layer of InAs over the last combination of a layer of GaAs and a layer of InAs. 
     
     
         22 . A semiconductor heterostructure with nanostructures formed according to the method of  claim 21 . 
     
     
         23 . A semiconductor heterostructure with nanostructures in a pattern formed according to the method of  claim 17 . 
     
     
         24 . A semiconductor heterostructure formed with nanostructures, comprising:
 (a) a first layer having a first surface and an opposite, second surface;   (b) a second layer having a first surface and an opposite, second surface, wherein the first layer is deposited over the second layer such that the second surface of the first layer is distant from the second layer;   (c) at least one indentation formed on the first surface of the first layer;   (d) a third layer deposited over the second surface of the first layer, wherein the third layer has a first surface and an opposite, second surface, and the third layer is deposited over the second surface of the first layer such that the second surface of the third layer is in contact with the second surface of the first layer; and   (e) at least one nanostructure formed on the first surface of the third layer and at a position corresponding to that of at least one indentation formed on the first surface of the first layer.   
     
     
         25 . The semiconductor heterostructure of  claim 24 , wherein the at least one indentation formed on the first surface of the first layer comprises one or more indentations formed in a pattern or an array. 
     
     
         26 . The semiconductor heterostructure of  claim 25 , wherein the at least one nanostructure comprises one or more nanostructures formed in a pattern or an array corresponding to the pattern or array the one or more indentations formed. 
     
     
         27 . The semiconductor heterostructure of  claim 26 , wherein the nanostructures comprise quantum dots, nanowires, nanorods, or nanotubes. 
     
     
         28 . The semiconductor heterostructure of  claim 24 , wherein the first to third layers comprise a GaAs layer, an AlAs layer and an InAs layer, respectively. 
     
     
         29 . A semiconductor heterostructure formed with nanostructures, comprising:
 (a) a first layer having a first surface and an opposite, second surface;   (b) at least one indentation formed on the first surface of the first layer;   (c) a second layer formed over the first surface of the first layer, wherein the second layer is a buffer layer;   (d) a layered structure formed over the second layer, wherein the layered structure has at least a first layer of a first semiconductor, a second layer of the first semiconductor, and a layer of a second semiconductor positioned between the first layer and the second layer of the first semiconductor; and   (e) at least one nanostructure formed on each of a first surface of the first layer and the second layer of the first semiconductor, respectively, and at a position corresponding to that of at least one indentation formed on the first surface of the first layer.   
     
     
         30 . The semiconductor heterostructure of  claim 29 , wherein the at least one indentation formed on the first surface of the first layer comprises one or more indentations formed in a pattern or an array. 
     
     
         31 . The semiconductor heterostructure of  claim 29 , wherein the at least one nanostructure comprises one or more nanostructures formed in a pattern or an array corresponding to the pattern or array the one or more indentations formed. 
     
     
         32 . The semiconductor heterostructure of  claim 31 , wherein the nanostructures comprise quantum dots, nanowires, nanorods, or nanotubes. 
     
     
         33 . The semiconductor heterostructure of  claim 29 , wherein the first layer comprises a layer of MBE GaAs or VGF GaAs, the second layer comprises a layer of GaAs, the first semiconductor comprises InAs, and the second semiconductor comprises GaAs, respectively. 
     
     
         34 . The semiconductor heterostructure of  claim 29 , comprising a super-lattice structure.