Electrostatic protection device for semiconductor circuit

Abstract

The electrostatic protection device includes a semiconductor substrate having a well formed therein. At least two sets of transistor fingers, for example the NMOS type, are spaced apart from each other. Each set of the MOS fingers includes multiple gates arranged in parallel to each other in one direction, and sources and drains alternately arranged at both sides of the gates in the semiconductor substrate. A well pickup surrounding every set of the transistor fingers and extending between any two set of the fingers is formed. Metal wires are connected to at least two portions of each of the drains and are also connected to an input/output pad to which Electrostatic Discharge (ESD) excessive current is introduced.

1 . An electrostatic protection device for a semiconductor circuit comprising:
 a semiconductor substrate having a well formed therein;   at least two sets of transistor fingers formed in at least two predetermined areas spaced apart from each other of the semiconductor substrate, each set of the transistor fingers comprising:   multiple gates arranged in parallel with respect to each other in one direction; and   sources and drains, wherein one source and one drain are alternately arranged at each side of each gate in the semiconductor substrate;   a well pickup surrounding every set of the transistor fingers such that any two sets of the transistor fingers are separated by a portion of the well pickup; and   metal wires connected to at least two portions of each of the drains and connected to an input/output pad to which electrostatic discharge (ESD) excessive current is introduced.   
   
   
       2 . The electrostatic protection device of  claim 1 , wherein the gates, the sources, and the drains in each set of the transistor fingers are arranged in the direction substantially parallel to the direction of the side of the pad to which the metal wires are connected. 
   
   
       3 . The electrostatic protection device of  claim 2 , wherein the well pickup is connected to either one or both ends of each of the sources. 
   
   
       4 . The electrostatic protection device of  claim 3 , wherein the metal wires are connected to both ends of each of the drains. 
   
   
       5 . The electrostatic protection device of  claim 4 , wherein each transistor finger is of an NMOS type.