Semiconductor integrated circuit device and radio frequency module
Abstract
The present invention provides a semiconductor integrated circuit device and a radio frequency module realizing reduction in high-order harmonic distortion or IMD. For example, a so-called antenna switch having a plurality of transistors between an antenna terminal and a plurality of signal terminals is provided with a voltage supply circuit. The voltage supply circuit is a circuit for supplying voltage from a voltage supply terminal to at least two signal terminals in the plurality of signal terminals via resistive elements. With the configuration, antenna voltage dropped due to a leakage or the like can be boosted and, for example, transistors in an off state can be set to a deep off state.
Claims
exact text as granted — not AI-modified1 . A semiconductor integrated circuit device comprising:
an antenna node coupled to an antenna; a voltage supply node to which bias voltage is applied; a plurality of signal nodes; a plurality of transistors coupled between the plurality of signal nodes and the antenna node and switching coupling/decoupling between the plurality of signal nodes and the antenna node; and a plurality of resistive elements each coupled between two or more signal nodes in the plurality of signal nodes and the voltage supply node.
2 . The semiconductor integrated circuit device according to claim 1 , wherein the number of the resistive elements is two, and each of the resistive elements is coupled between the two signal nodes out of the plurality of signal nodes and the voltage supply node.
3 . The semiconductor integrated circuit device according to claim 2 , wherein two signal nodes out of the plurality of signal nodes are signal nodes to/from which signals of relatively low power and/or low frequency are input/output.
4 . The semiconductor integrated circuit device according to claim 1 , wherein the resistance value of each of the resistive elements is 100 kΩ to 200 kΩ.
5 . The semiconductor integrated circuit device according to claim 1 , wherein each of the plurality of transistors is constructed by transistor elements in a plurality of stages coupled in series.
6 . A radio frequency module comprising:
an antenna node coupled to an antenna; a voltage supply node to which bias voltage is applied; a plurality of transmission nodes for transmission signals of a plurality of communication methods; a plurality of reception nodes for reception signals of the plurality of communication methods; a common node; a plurality of transmission transistors each coupled between the transmission nodes and the antenna node and switching coupling/decoupling between the transmission nodes and the antenna node; a common transistor coupled between the antenna node and the common node and switching coupling/decoupling between the antenna node and the common node; a plurality of reception transistors each coupled between the reception nodes and the common node and switching coupling/decoupling between the reception nodes and the common node; a first resistive element coupled between a first node as one of the transmission nodes and the voltage supply node; and a second resistive element coupled between the common node and the voltage supply node.
7 . The radio frequency module according to claim 6 , wherein the first node is conformed with a communication method of small transmission power and/or low frequency band among the plurality of communication methods.
8 . The radio frequency module according to claim 7 ,
wherein the communication modes include a W-CDMA method using a low frequency band and a W-CDMA method using a frequency band higher than the low frequency band, and wherein the first node is conformed with the W-CDMA method using the low frequency band.
9 . The radio frequency module according to claim 6 , wherein the resistance value of each of the first and second resistive elements is 100 kΩ to 150 kΩ.
10 . The radio frequency module according to claim 6 , wherein each of the transmission transistors and the common transistor is constructed by triple-gate transistor elements in two stages coupled in series.Cited by (0)
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