Non-volatile semiconductor storage device

Abstract

This non-volatile semiconductor storage device includes a flip-flop in which two inverters, each consisting of a load transistor and a storage transistor connected in series, are cross-connected; and two gate transistors, each respectively connected to a node of the flip-flop on a side thereof. The storage transistors of the inverters are constituted by storage transistors which can be threshold voltage controlled by injection of electrons into the neighborhood of their gates. This non-volatile semiconductor storage device further includes two bit lines, each of which is connected to a respective one of the two gate transistors; a word line which is connected to both of the gate electrodes of the two gate transistors; a first voltage supply line which is connected to the sources of the storage transistors of the inverters; and a second voltage supply line which is connected to the sources of the load transistors of the inverters.

1 . A non-volatile semiconductor storage device, comprising:
 a flip-flop in which two inverters, each consisting of a load transistor and a storage transistor connected in series, are cross-connected;   two gate transistors, each respectively connected to a node of said flip-flop on a side thereof;   two bit lines, each of which is connected to a respective one of said two gate transistors, and which are controlled to a voltage between operating power supply voltage and ground voltage;   a word line which is connected to both of the gate electrodes of said two gate transistors, and which is controlled to a voltage between operating power supply voltage and ground voltage;   a first voltage supply line which is connected to the sources of said storage transistors of said inverters, and to which a predetermined first voltage is supplied during writing and during erasure; and   a second voltage supply line which is connected to the sources of said load transistors of said inverters, and to which a predetermined second voltage is supplied during writing; wherein said storage transistors of said inverters are constituted by storage transistors which can be threshold voltage controlled by injection of electrons into the neighborhood of their gates.   
   
   
       2 . A non-volatile semiconductor storage device according to  claim 1 , wherein each of said storage transistor comprises:
 an insulation layer side spacer which is formed at a side portion of its gate electrode; and   a low impurity density region which is formed at a border portion of its drain; and wherein:   during writing, said first voltage supply line applies said first voltage to the sources of said storage transistors, and said second voltage supply line applies said second voltage to the gates of said storage transistors via the sources of said load transistors; and thereby information is written into said storage transistors by channel hot electrons being injected into said insulation layer side spacers; and   during erasure, said first voltage supply line applies said first voltage to the sources of said storage transistors; and thereby information which is stored in said storage transistors is erased by an avalanche of hot holes being injected into said insulation layer side spacers.   
   
   
       3 . A non-volatile semiconductor storage device according to  claim 1 , wherein each said inverter comprises a transistor for pre-charge which is connected in parallel with said load transistor thereof; and
 further comprising pre-charge control voltage supply lines which supply pre-charge control voltages to the gates of said transistors for pre-charge; and   wherein said transistors for pre-charge are ON/OFF controlled independently from said load transistors by said pre-charge control voltages supplied by said pre-charge control voltage supply lines.   
   
   
       4 . A non-volatile semiconductor storage device according to  claim 3 , wherein said second voltage supply line is provided separately for each of said inverters. 
   
   
       5 . A non-volatile semiconductor storage device according to  claim 3 , wherein said first voltage supply line is provided separately for each of said inverters. 
   
   
       6 . A non-volatile semiconductor storage device according to  claim 1 , wherein the continuity resistances of the load transistors of said two inverters are unbalanced. 
   
   
       7 . A non-volatile semiconductor storage device according to  claim 1 , wherein the electrostatic capacitances with respect to the power supply voltage lines, or with respect to ground, of said two inverters are unbalanced. 
   
   
       8 . A non-volatile semiconductor storage device according to  claim 1 , wherein the continuity resistances of the storage transistors of said two inverters are unbalanced. 
   
   
       9 . A method for determining the state of a non-volatile semiconductor storage device according to  claim 3 , comprising a step of supplying a pre-charge control voltage selectively to one only of said pre-charge control voltage supply lines, and thereby turning only one but not the other of said transistors for pre-charge of said two inverters ON, thus forcibly determining the state of said flip-flop. 
   
   
       10 . A method for determining the state of a non-volatile semiconductor storage device according to  claim 4 , comprising:
 a step of supplying a voltage lower than said first voltage to said first voltage supply line, and thereby raising the source potentials of said storage transistors of said two inverters and turning said storage transistors OFF;   a step of supplying different voltages to said second voltage supply lines, thereby applying pre-charge voltages of different potentials to said nodes via said transistors for pre-charge of said two inverters; and   a step of gradually decreasing said low voltage supplied to said first voltage supply line, thereby gradually lowering the source potentials of said storage transistors of said two inverters.   
   
   
       11 . A method for determining the state of a non-volatile semiconductor storage device according to  claim 4 , comprising:
 a step of supplying voltages lower than said first voltage to said first voltage supply lines, and thereby raising the source potentials of said storage transistors of said two inverters and turning said storage transistors OFF;   a step of supplying the same voltage to said second voltage supply lines, thereby applying pre-charge voltages of the same potential to said nodes via said transistors for pre-charge of said two inverters; and   a step of gradually decreasing said low voltages supplied to said first voltage supply lines while maintaining a predetermined potential difference therebetween, thereby gradually lowering the source potentials of said storage transistors of said two inverters while maintaining a predetermined potential difference therebetween.   
   
   
       12 . A semiconductor integrated circuit device comprising a non-volatile semiconductor storage device as described in  claim 1 , a circuit which may require repair comprising a portion which may require repair, and a redundancy circuit which serves as an alternative to said circuit which may require repair; and
 wherein said non-volatile semiconductor storage device is a storage circuit which stores repair information specifying which circuit may require repair by said redundancy circuit serving as an alternative thereto.   
   
   
       13 . A semiconductor integrated circuit device comprising a non-volatile semiconductor storage device as described in  claim 1 , an analog circuit, and a constant trimming circuit which adjusts a circuit constant of said analog circuit; and
 wherein said non-volatile semiconductor storage device is a storage circuit which stores information in said constant trimming circuit for specifying said circuit constant.   
   
   
       14 . A semiconductor integrated circuit device comprising a non-volatile semiconductor storage device as described in  claim 1 , an oscillation circuit, and a frequency trimming circuit which adjusts the oscillation frequency of said oscillation circuit;
 and wherein said non-volatile semiconductor storage device is a storage circuit which stores information in said frequency trimming circuit for specifying said oscillation frequency.   
   
   
       15 . A semiconductor integrated circuit device comprising a non-volatile semiconductor storage device as described in  claim 1 , a reference voltage generation circuit, and a voltage trimming circuit which adjusts the reference voltage generated by said reference voltage generation circuit;
 and wherein said non-volatile semiconductor storage device is a storage circuit which stores information in said voltage trimming circuit for specifying said reference voltage.   
   
   
       16 . A semiconductor integrated circuit device comprising a non-volatile semiconductor storage device as described in  claim 1 , and a security circuit which identifies a chip in which said semiconductor integrated circuit device is mounted; and
 wherein said non-volatile semiconductor storage device is a storage circuit which stores information in said security circuit for specifying said chip.