Dual gate oxide structure in semiconductor device and method thereof

Abstract

In the method of manufacturing a dual gate oxide layer of a semiconductor device, which has first and second active regions operating at mutually different voltages on a semiconductor substrate, the first and second active regions having a device isolation layer of STI (Shallow Trench Isolation) structure; the method of manufacturing the dual gate insulation layer includes, forming the device isolation layer so that an uppermost part thereof is positioned lower than an upper surface of the first and second active regions, before forming a gate insulation layer corresponding to each of the first and second active regions. Whereby, it is be effective till a portion of trench sidewall utilized as the active region, to increase a cell current of the active region and to prevent a stringer caused by a stepped coverage between the active region and a field region and a dent caused on a boundary face between the active region and the field region.

1 . A method of manufacturing a dual gate insulation layer of a semiconductor device which has first and second active regions operating at mutually different voltages on a semiconductor substrate, said first and second active regions having a device isolation layer of STI (Shallow Trench Isolation) structure, said method comprising: 
 forming the device isolation layer so that an uppermost part of the device isolation layer is positioned lower than an upper surface of the first and second active regions, before forming a gate insulation layer corresponding to each of the first and second active regions.    
   
   
       2 . A dual gate oxide structure in a semiconductor device having first and second active regions operating at mutually different voltages and a device isolation layer of STI structure, said structure comprising: 
 a device isolation layer for isolating between the first and second active regions, isolating between respective transistor devices provided with the first and second active regions, an upper surface of said device isolation layer being formed lower than an upper surface of the first and second active regions;    a first gate oxide layer formed on an upper surface of the first active region and on an STI sidewall in which the device isolation layer within the first active region is partially filled; and    a second gate oxide layer formed on an upper surface of the second active region and on an STI sidewall in which the device isolation layer within the second active region is partially filled.    
   
   
       3 . The dual gate oxide structure of  claim 1 , wherein the first active region is a low voltage region.  
   
   
       4 . The dual gate oxide structure of  claim 1 , wherein an uppermost part of the device isolation layer is positioned below by about 200 Å through 300 Å from an upper surface of the first and second active regions.