Chip stack package

Abstract

Provided is a chip stack package that may include a lower semiconductor chip, an upper semiconductor chip stacked on the lower semiconductor chip, and at least one adhesive formed in space between the lower semiconductor chip and the upper semiconductor chip. The at least one adhesive may include a first adhesive and a second adhesive. The first adhesive may be formed in a portion of the space, and the second adhesive may be formed in the space except for a region in which the first adhesive is provided. The space between adjacent semiconductor chips may be completely filled with the at least one adhesive. Therefore, a chip stack package according to the exemplary embodiments of the present invention may exhibit improved mechanical stability and reliability.

1 . A chip stack package including: 
 a first semiconductor chip;    a second semiconductor chip stacked on the first semiconductor chip;    connector for electrically connecting the first semiconductor chip to the second semiconductor chip; and    at least one adhesive formed in a space between the first semiconductor chip and the second semiconductor chip, the at least one adhesive including a first adhesive and a second adhesive, the first adhesive being formed in a peripheral region on which the connector is provided, the second adhesive being formed in the space remaining between the first semiconductor chip and the second semiconductor chip except for a region in which the first adhesive is provided.    
     
     
         2 . The chip stack package according to  claim 1 , wherein the first semiconductor chip includes a plurality of first conductive connectors and the second semiconductor chip includes a plurality of second conductive connectors, and the first conductive connectors are electrically connected to corresponding second conductive connectors through the connector.  
     
     
         3 . The chip stack package according to  claim 2 , wherein the first conductive connectors are formed in a peripheral region of the first semiconductor chip and the second conductive connectors are formed in a peripheral region of the second semiconductor chip.  
     
     
         4 . The chip stack package according to  claim 2 , wherein the first conductive connectors are formed in a central region of the first semiconductor chip and the second conductive connectors are formed in a central region of the second semiconductor chip.  
     
     
         5 . The chip stack package according to  claim 2 , wherein the first and second conductive connectors are through electrodes.  
     
     
         6 . The chip stack package according to  claim 5 , wherein the connector is conductive protrusions formed on at least one end of the first and second conductive connectors.  
     
     
         7 . The chip stack package according to  claim 6 , wherein the conductive protrusions are conductive bumps.  
     
     
         8 . The chip stack package according to  claim 1 , wherein the first adhesive is formed by curing a flowable adhesive composition and the second adhesive is a solid adhesive.  
     
     
         9 . The chip stack package according to  claim 1 , wherein the first adhesive has the material properties different from the second adhesive.  
     
     
         10 . The chip stack package according to  claim 3 , wherein the second adhesive covers at least a central region of the first semiconductor chip.  
     
     
         11 . The chip stack package according to  claim 8 , wherein the second adhesive is a multi-layer adhesive tape.  
     
     
         12 . The chip stack package according to  claim 11 , wherein the multi-layer adhesive tape includes a core layer between an upper adhesive layer and a lower adhesive layer.  
     
     
         13 . A chip stack package including: 
 a substrate having an upper surface and a lower surface;    a first semiconductor chip stacked on the upper surface of the substrate;    a second semiconductor chip stacked on the first semiconductor chip;    connector for electrically connecting the substrate to the first semiconductor chip and the first semiconductor chip to the second semiconductor chip; and    at least one adhesive formed in spaces between the substrate and the first semiconductor chip and between the first semiconductor chip and the second semiconductor chip, the at least one adhesive including a first adhesive and a second adhesive, the first adhesive being formed in a peripheral region on which the connector is provided, the second adhesive being formed in the spaces except for a region in which the first adhesive is provided.    
     
     
         14 . The chip stack package according to  claim 13 , wherein the substrate has a plurality of substrate pads, the first semiconductor chip includes a plurality of first conductive connectors and the second semiconductor chip includes a plurality of second conductive connectors, and the substrate pads are electrically connected to the first conductive connectors through the connector and the first conductive connectors are electrically connected to the second conductive connectors through the connector.  
     
     
         15 . The chip stack package according to  claim 14 , wherein the first conductive connectors are formed in a peripheral region of the first semiconductor chip and the second conductive connectors are formed in a peripheral region of the second semiconductor chip.  
     
     
         16 . The chip stack package according to  claim 14 , wherein the first conductive connectors are formed in a central region of the first semiconductor chip and the second conductive connectors are formed in a central region of the second semiconductor chip.  
     
     
         17 . The chip stack package according to  claim 14 , wherein the first and second conductive connectors are through electrodes.  
     
     
         18 . The chip stack package according to  claim 17 , wherein the connector is conductive protrusions formed on at least one end of the first and second conductive connectors.  
     
     
         19 . The chip stack package according to  claim 18 , wherein the conductive protrusions are conductive bumps.  
     
     
         20 . The chip stack package according to  claim 13 , wherein the first adhesive is formed by curing a flowable adhesive composition and the second adhesive is a solid adhesive.  
     
     
         21 . The chip stack package according to  claim 13 , wherein the second adhesive includes a substrate attaching adhesive for attaching the substrate to the first semiconductor chip and a chip attaching adhesive for attaching the second semiconductor chip to the first semiconductor chip.  
     
     
         22 . The chip stack package according to  claim 13 , wherein the first adhesive has the material properties different from the second adhesive.  
     
     
         23 . The chip stack package according to  claim 15 , wherein the second adhesive covers at least central regions of the substrate and the first semiconductor chip.  
     
     
         24 . The chip stack package according to  claim 20 , wherein the second adhesive is a multi-layer adhesive tape.  
     
     
         25 . The chip stack package according to  claim 24 , wherein the multi-layer adhesive tape includes a core layer between an upper adhesive layer and a lower adhesive layer.  
     
     
         26 . The chip stack package according to  claim 13 , further including external connection terminals formed on the lower surface of the substrate.