Integrated circuit devices having corrosion resistant fuse regions and methods of fabricating the same

Abstract

Integrated circuit devices are provided including an integrated circuit substrate and first through fourth spaced apart lower interconnects on the integrated circuit substrate. The third and fourth spaced apart lower interconnects are parallel to the first and second lower interconnects. A first fuse is provided on the first and second lower interconnects between the first and second lower interconnects and is electrically coupled to the first and second lower interconnects. A second fuse is provided spaced apart from the first fuse and on the third and fourth lower interconnects. The second fuse is between the third and fourth lower interconnects and is electrically coupled to the third and fourth lower interconnects. Related methods of fabricating integrated circuit devices are also provided.

1 . A fuse region of an integrated circuit device comprising: 
 an integrated circuit substrate;    a plurality of spaced apart fuses on the integrated circuit substrate; and    a fuse guard ring on the integrated circuit substrate that surrounds the plurality of fuses.    
   
   
       2 . The fuse region of  claim 1  wherein the fuse guard ring comprises: 
 an intermediate interconnect guard ring having a surface that is substantially planar to surfaces of the plurality of fuse regions;    a first metal guard ring plug on the intermediate interconnect guard ring;    a first metal guard ring on the first metal guard ring plug;    a second metal guard ring plug on the first metal guard ring; and    a second metal guard ring on the second metal guard ring plug.    
   
   
       3 . An integrated circuit device comprising: 
 an integrated circuit substrate including first and second regions;    a lower interlayer insulating layer on the integrated circuit substrate;    a plurality of parallel lower interconnects on the integrated circuit substrate, odd-numbered ones of the plurality lower interconnects being in the first region of the integrated circuit substrate and even-numbered ones of the plurality of lower interconnects being in the second region of the integrated circuit substrate;    a plurality of parallel fuses on the plurality of lower interconnects, even-numbered ones of the plurality of fuses being in the first region of the integrated circuit substrate and electrically coupled to respective even-numbered ones of the plurality of lower interconnects and odd-numbered ones of the plurality of fuses being in the second region of the integrated circuit substrate and electrically coupled to respective odd-numbered ones of the plurality of lower interconnects;    a plurality of upper interconnects on the plurality of parallel fuses, a first group of the plurality of upper interconnects being electrically coupled the odd-numbered ones of the plurality of lower interconnects and the even-numbered ones of the plurality of fuses and a second group of the plurality of upper interconnects being electrically coupled to the even-numbered ones of the plurality of lower interconnects and to the odd-numbered ones of the plurality of fuses.    
   
   
       4 . The integrated circuit device of  claim 3  further comprising: 
 an intermediate insulating layer on the plurality of lower interconnects;    an upper insulating layer on the plurality of fuses;    a plurality of odd-numbered intermediate interconnects on the odd numbered ones of the plurality of lower interconnects that are adjacent to the first region of the integrated circuit substrate, the plurality of odd-numbered intermediate interconnects being interposed between the intermediate interlayer insulating layer and the upper interlayer insulating layer; and    a plurality of even-numbered intermediate interconnects on the even numbered ones of the plurality of lower interconnects that are adjacent to the second region, the plurality of even-numbered intermediate interconnects being interposed between the intermediate interlayer insulating layer and the upper interlayer insulating layer, wherein the odd-numbered ones of the plurality of upper interconnects are electrically coupled to the plurality of odd-numbered lower interconnects through the plurality of odd-numbered intermediate interconnects and wherein the even-numbered ones of the plurality of upper interconnects are electrically coupled to the plurality of even-numbered lower interconnects through the plurality of even-numbered intermediate interconnects.    
   
   
       5 . The integrated circuit device of  claim 4  wherein the plurality of odd-numbered intermediate interconnects, the plurality of even-numbered intermediate interconnects and the plurality of fuses comprise the same material layer.  
   
   
       6 . The integrated circuit device of  claim 5  wherein the first group of upper interconnects are adjacent to the first region of the integrated circuit substrate and opposite the second region of the integrated circuit substrate and wherein the second group of upper interconnects are adjacent to the second region of the integrated circuit substrate and opposite the first region of the integrated circuit substrate.  
   
   
       7 . The integrated circuit device of  claim 4  wherein the even-numbered ones of the plurality of fuses are on extension lines of the even-numbered ones of the plurality of lower interconnects and the odd-numbered ones of the plurality of fuses are on extension lines of the odd-numbered ones of the plurality of lower interconnects.  
   
   
       8 . The integrated circuit device of  claim 4  wherein the plurality of lower interconnects comprise non-corrosive material layers.  
   
   
       9 . The integrated circuit device of  claim 8  wherein the non-corrosive material layer comprises at least one of a polysilicon layer and a tungsten polycide layer.  
   
   
       10 . The integrated circuit device of  claim 4  wherein the plurality of fuses comprise tungsten layers.  
   
   
       11 . An integrated circuit device comprising: 
 an integrated circuit substrate having first and second regions;    a plurality of parallel lower interconnects, odd-numbered ones of the plurality of lower interconnects being in the first region of the integrated circuit substrate and even-numbered ones of the plurality of lower interconnects being in the second region of the integrated circuit substrate;    a plurality of fuses on the first and second regions of the integrated circuit substrate, the plurality of fuses having overlap portions with the plurality of lower interconnects; and    a plurality of upper interconnects, a first group of the plurality of upper interconnects being electrically coupled to ends of ones of the plurality of fuses adjacent to the first region of the integrated circuit substrate, a second group of the plurality of upper interconnects being electrically coupled to ends of ones of the plurality of fuses adjacent to the second region of the integrated circuit substrate, ends of the overlap portions of the plurality of fuses being electrically coupled to ends of the plurality of lower interconnects thereunder.    
   
   
       12 . The integrated circuit device of  claim 11  wherein the plurality of lower interconnects comprise non-corrosive material layers.  
   
   
       13 . The integrated circuit device of  claim 12  wherein the non-corrosive material layer comprises at least one of a polysilicon layer and a polycide layer.  
   
   
       14 . The integrated circuit device of  claim 11  wherein the plurality of fuses comprise tungsten layers.  
   
   
       15 . A method of forming an integrated circuit device comprising: 
 forming first through fourth spaced apart lower interconnects on an integrated circuit substrate, the third and fourth spaced apart lower interconnects being parallel to the first and second lower interconnects;    forming a first fuse on the first and second lower interconnects, the first fuse being between the first and second lower interconnects and electrically coupled to the first and second lower interconnects; and    forming a second fuse, spaced apart from the first fuse, on the third and fourth lower interconnects, the second fuse being between the third and fourth lower interconnects and electrically coupled to the third and fourth lower interconnects.    
   
   
       16 . The method of  claim 15 , further comprising forming first, second and third intermediate interconnects on the integrated circuit substrate having surfaces that are substantially planar with surfaces of the first and second fuses, wherein the first intermediate interconnect is on the first lower interconnect and electrically coupled to the first lower interconnect, wherein the second intermediate interconnect is on the second and fourth lower interconnects and is electrically coupled to the second and fourth lower interconnects and wherein the third intermediate interconnect is on the third lower interconnect and is electrically coupled to the third lower interconnect.  
   
   
       17 . The method of  claim 16 , further comprising forming first, second and third lower metal interconnects on the first, second and third intermediate interconnects, respectively, and electrically coupled to the first, second and third intermediate interconnects, respectively.  
   
   
       18 . The method of  claim 16 , further comprising forming a fuse guard ring on the integrated circuit substrate that surrounds the first and second fuses.  
   
   
       19 . The method of  claim 18 , wherein forming the fuse guard ring comprises: 
 forming an intermediate interconnect guard ring between the first and second fuses and the first, second and third intermediate interconnects;    forming a first metal guard ring plug on the intermediate interconnect guard ring;    forming a first metal guard ring on the first metal guard ring plug;    forming a second metal guard ring plug on the first metal guard ring; and    forming a second metal guard ring on the second metal guard ring plug.    
   
   
       20 . The method of  claim 16 , further comprising forming first, second, third and fourth fuse contact plugs, wherein the first fuse is electrically coupled to the first and second lower interconnects through the first and second fuse contact plugs and wherein the second fuse is electrically coupled to the third and fourth lower interconnects through the third and fourth fuse contact plugs.  
   
   
       21 . The method of  claim 20  wherein the forming the first, second, third and fourth fuse contact plugs comprise forming a barrier metal layer and forming a metal plug layer on the barrier metal layer.  
   
   
       22 . A method of forming a fuse region comprising: 
 forming a plurality of spaced apart fuses on an integrated circuit substrate; and    forming a fuse guard ring on the integrated circuit substrate that surrounds the plurality of fuses.    
   
   
       23 . The method of  claim 22  wherein forming the fuse guard ring comprises: 
 forming an intermediate interconnect guard ring having a surface that is substantially planar to surfaces of the plurality of fuse regions;    forming a first metal guard ring plug on the intermediate interconnect guard ring;    forming a first metal guard ring on the first metal guard ring plug;    forming a second metal guard ring plug on the first metal guard ring; and    forming a second metal guard ring on the second metal guard ring plug.    
   
   
       24 . A method of forming an integrated circuit comprising: 
 forming a lower interlayer insulating layer on an integrated circuit substrate including first and second regions;    forming a plurality of parallel lower interconnects on the integrated circuit substrate, odd-numbered ones of the plurality lower interconnects being in the first region of the integrated circuit substrate and even-numbered ones of the plurality of lower interconnects being in the second region of the integrated circuit substrate;    forming a plurality of parallel fuses on the plurality of lower interconnects, even-numbered ones of the plurality of fuses being in the first region of the integrated circuit substrate and electrically coupled to respective even-numbered ones of the plurality of lower interconnects and odd-numbered ones of the plurality of fuses being in the second region of the integrated circuit substrate and electrically coupled to respective odd-numbered ones of the plurality of the lower interconnects; and    forming a plurality of upper interconnects on the plurality of parallel fuses, a first group of the plurality of upper interconnects being electrically coupled the odd-numbered ones of the lower interconnects and the even-numbered ones of the plurality of fuses and a second group of the plurality of upper interconnects being electrically coupled to the even-numbered ones of the plurality of lower interconnects and to the odd-numbered ones of the plurality of fuses.    
   
   
       25 . The method of  claim 24  further comprising: 
 forming an intermediate insulating layer on the plurality of lower interconnects;    forming an upper insulating layer on the plurality of fuses;    forming a plurality of odd-numbered intermediate interconnects on the odd-numbered ones of the plurality of lower interconnects that are adjacent to the first region of the integrated circuit substrate, the plurality of odd-numbered intermediate interconnects being interposed between the intermediate interlayer insulating layer and the upper interlayer insulating layer; and    forming a plurality of even-numbered intermediate interconnects on the even numbered ones of the plurality of lower interconnects that are adjacent to the second region, the even-numbered intermediate interconnects being interposed between the intermediate interlayer insulating layer and the upper interlayer insulating layer, wherein the odd-numbered ones of the plurality of upper interconnects are electrically coupled to the plurality of odd-numbered lower interconnects through the plurality of odd-numbered intermediate interconnects and wherein the even-numbered ones of the plurality of upper interconnects are electrically coupled to the plurality of even-numbered lower interconnects through the plurality of even-numbered intermediate interconnects.    
   
   
       26 . A method of forming integrated circuit devices comprising: 
 forming a plurality of parallel lower interconnects, odd-numbered ones of the plurality of lower interconnects being in the first region of an integrated circuit substrate and even-numbered ones of the plurality of lower interconnects being in a second region of the integrated circuit substrate;    forming a plurality of fuses on the first and second regions of the integrated circuit substrate, the plurality of fuses having overlap portions with the plurality of lower interconnects; and    forming a plurality of upper interconnects, a first group of the plurality of upper interconnects being electrically coupled to ends of ones of the plurality of fuses adjacent to the first region of the integrated circuit substrate, a second group of the plurality of upper interconnects being electrically coupled to ends of ones of the plurality of fuses adjacent to the second region, ends of the overlap portions of the plurality of fuses being electrically coupled to ends of the plurality of lower interconnects thereunder.    
   
   
       27 . An integrated circuit device comprising: 
 an integrated circuit substrate having first and second regions;    a plurality of parallel fuses over the integrated circuit substrate, the fuses including odd-numbered fuses and even-numbered fuses between the odd-numbered fuses, each of the fuses being disposed across the first and second regions;    a plurality of odd-numbered lower interconnects between the odd-numbered fuses and the integrated circuit substrate, the odd-numbered lower interconnects being disposed in the first region to be parallel with the odd-numbered fuses, and both ends of each of the odd-numbered lower interconnects being electrically coupled to two positions of an odd-numbered lower interconnect thereon; and    a plurality of even-numbered lower interconnects between the even-numbered fuses and the integrated circuit substrate, the even-numbered lower interconnects being disposed in the second region to be parallel with the even-numbered fuses, and both ends of each of the even-numbered lower interconnects being electrically coupled to two positions of an even-numbered lower interconnect thereon.    
   
   
       28 . The integrated circuit device of  claim 27 , further comprising a plurality of upper interconnects on the fuses, wherein the upper interconnects are electrically coupled to both ends of the fuses.  
   
   
       29 . The integrated circuit device of  claim 27 , wherein the lower interconnects comprise non-corrosive material layers.  
   
   
       30 . The integrated circuit device of  claim 29 , wherein the non-corrosive material layer comprises at least one of a polysilicon layer and a polycide layer.  
   
   
       31 . The integrated circuit device of  claim 27 , wherein the fuses comprise tungsten layers.