Semiconductor integrated circuit device, method of testing the same, database for design of the same and method of designing the same

Abstract

Elements of a combinational circuit are divided into plural groups. The output from a terminal Q is fixed at shifted timing in flip-flop circuits belonging to each of groups X, Y and Z resulting from this grouping. With the outputs from the terminals Q of the flip-flop circuits thus fixed, an operation of a shift mode is carried out. When the operation of the shift mode is completed, a hold releasing operation and a capture operation are carried out with respect to each of the groups of the flip-flop circuits. For example, the hold releasing operation is carried out when one clock is at a high level with the capture operation carried out when the clock is at a low level, or the hold releasing operation is successively carried out with respect to each of the groups and then the capture operation for capturing a data signal is carried out with respect to each of the groups.

1 - 19 . (canceled)  
   
   
       20 . A database for use in design of an integrated circuit device comprising plural cores each storing data necessary for designing said integrated circuit device, said database including information regarding power consumption of said cores during a test.  
   
   
       21 . The database for use in design of an integrated circuit device of  claim 20 , 
 wherein said information regarding power consumption during a test includes at least one of:    an estimated value of peak power consumption of each of said cores;    an estimated maximum transition number of states of each of said cores, a circuit scale of each of said cores and power consumption of gates included in each of said cores; and    a circuit and a simulation pattern.    
   
   
       22 . The database for use in design of an integrated circuit device of  claim 21 , 
 wherein said database includes information regarding a possible division number of each of said cores.    
   
   
       23 . The database for use in design of an integrated circuit device of  claim 22 , 
 wherein said information regarding a possible division number of each of said cores includes at least one of:    a level at which power consumption during a shift operation is equal to peak power consumption in dividing said core;    a division number and power consumption of a core not accompanied by change in design of a test circuit; and    a division number and peak power consumption in every clock of a core not accompanied by change in design of a test circuit.    
   
   
       24 . The database for use in design of an integrated circuit device of  claim 20 , 
 wherein said database includes information regarding division probability of each of said cores.    
   
   
       25 . The database for use in design of an integrated circuit device of  claim 24 , 
 wherein said information regarding division probability of each of said cores includes at least one of a maximum possible division number of said core and a number of clock systems.