Field effect transistor and method for manufacturing the same

Abstract

A field effect transistor (FET) and a method for manufacturing the same, in which the FET may include an isolation film formed on a semiconductor substrate to define an active region, and a gate electrode formed on a given portion of the semiconductor substrate. A channel layer may be formed on a portion of the gate electrode, with source and drain regions formed on either side of the channel layer so that boundaries between the channel layer and the source and drain regions of the FET may be perpendicular to a surface of the semiconductor substrate.

1 . A field effect transistor (FET), comprising: 
 a semiconductor substrate having an isolation film formed thereon to define an active region;    a gate electrode formed on a given portion of the semiconductor substrate;    a channel layer formed on a portion of the gate electrode; and    source and drain regions formed on either side of the channel layer so that boundaries between the channel layer and the source and drain regions are perpendicular to a surface of the semiconductor substrate.    
   
   
       2 . The FET of  claim 1 , wherein the channel layer is a non-doped epitaxial layer.  
   
   
       3 . The FET of  claim 1 , wherein the channel layer is an epitaxial layer having an n-type or p-type impurity.  
   
   
       4 . The FET of  claim 1 , wherein a boundary between source region and one side of the channel layer or between the drain region and the other side of the channel layer aligns with a corresponding sidewall of the gate electrode.  
   
   
       5 . The FET of  claim 1 , wherein the source and drain regions are formed of an epitaxial layer having a doped impurity.  
   
   
       6 . The FET of  claim 1 , wherein surfaces of the source and drain regions rise up a surface of the channel layer.  
   
   
       7 . The FET of  claim 6 , further comprising a pair of insulating spacers, one insulating spacer formed on each side of the gate electrode.  
   
   
       8 . The FET of  claim 1 , further comprising: 
 a gate oxide layer formed between the channel layer and the gate electrode.    
   
   
       9 . The FET of  claim 1 , further comprising: 
 a storage node formed between the channel layer and the gate electrode.    
   
   
       10 . The FET of  claim 9 , wherein the storage node is a stacked structure including a gate oxide layer, a floating gate and an inter gate insulating layer.  
   
   
       11 . The FET of  claim 9 , wherein the storage node is one of an oxide-nitride-oxide (ONO) layer and a nano-crystal layer.  
   
   
       12 . The FET of  claim 1 , further comprising: 
 a high mobility material formed between the channel layer and the gate electrode.    
   
   
       13 . The FET of  claim 12 , wherein the high mobility material is a layer or stacked structure selected from the group consisting of C, Si, Ge and combinations thereof.  
   
   
       14 . The FET of  claim 1 , wherein 
 the channel layer has a width and a length,    a surface of the isolation film disposed on either side of the channel layer in a width direction of the channel layer is lower than a bottom surface of the channel layer, and    the gate electrode encloses upper and side surfaces of the channel layer.    
   
   
       15 . The FET of  claim 1 , further comprising; 
 a silicide layer formed on a surface of the gate electrode and surfaces of the source and drain regions.    
   
   
       16 . The FET of  claim 15 , wherein 
 a surface of the isolation film formed on side portions of the source and drain regions is positioned between a top surface and a bottom surface of the source and drain regions, and    the silicide layer is formed on upper and side surfaces of the source and drain regions.    
   
   
       17 . The FET of  claim 1 , wherein the channel layer is formed on a lower portion of the gate electrode.  
   
   
       18 . A field effect transistor (FET), comprising: 
 a semiconductor substrate having an isolation film formed thereon to define an active region;    a channel layer formed on a portion of the active region and having a width and a length;    a gate electrode formed on the channel layer so as to extend in the width direction of the channel layer;    source and drain regions disposed on corresponding sides of the channel layer in a length direction of the channel layer so that boundaries between the channel layer and the source and drain regions are perpendicular to a surface of the semiconductor substrate; and    a pair of insulating spacers, one insulating spacer formed on each sidewall of the gate electrode.    
   
   
       19 . The FET of  claim 18 , wherein 
 a surface of the isolation film disposed on either side of the channel layer in a width direction of the channel layer is lower than a bottom surface of the channel layer, and    the gate electrode encloses upper and side surfaces of the channel layer.    
   
   
       20 . The FET of  claim 18 , wherein the source and drain regions are formed of an epitaxial layer having a doped impurity.  
   
   
       21 . The FET of  claim 18 , wherein a boundary between source region and one side of the channel layer or between the drain region and the other side of the channel layer substantially aligns with a corresponding outer side surface of a spacer.  
   
   
       22 . The FET of  claim 18 , further comprising a high mobility material formed between the channel layer and the gate electrode.  
   
   
       23 . The FET of  claim 18 , wherein the high mobility material is a layer or stacked structure selected from the group consisting of C, Si, Ge and combinations thereof.  
   
   
       24 . The FET of  claim 18 , further comprising a gate oxide layer formed between the channel layer and the gate electrode.  
   
   
       25 . The FET of  claim 18 , further comprising a storage node formed between the channel layer and the gate electrode.  
   
   
       26 . The FET of  claim 25 , wherein the storage node is a stacked structure including a gate oxide layer, a floating gate and an inter gate insulating layer.  
   
   
       27 . The FET of  claim 25 , wherein the storage node is one of an oxide-nitride-oxide (ONO) layer and a nano-crystal layer.  
   
   
       28 . The FET of  claim 18 , wherein the channel layer is formed on an upper portion of the active region.  
   
   
       29 . A method for manufacturing a field effect transistor (FET), comprising: 
 forming a junction layer on a semiconductor substrate;    forming an isolation film on a given portion of the semiconductor substrate;    forming source and drain regions with a space between the source and drain regions in the junction layer;    forming a channel layer in the space; and    forming a gate electrode on the channel layer.    
   
   
       30 . The method of  claim 29 , wherein forming source and drain regions with a space between further includes anisotrophically etching a given portion of the junction layer to define the source and drain regions with the space there between.  
   
   
       31 . The method of  claim 29 , wherein forming the junction layer includes: 
 implanting impurities for a source and a drain into a surface of the semiconductor substrate; and    activating the impurities.    
   
   
       32 . The method of  claim 29 , wherein the forming the junction layer includes: 
 growing an epitaxial layer on a surface of the semiconductor substrate; and    doping impurities for a source and a drain into the epitaxial layer.    
   
   
       33 . The method of  claim 29 , wherein forming the junction layer includes growing an epitaxial layer that includes doped impurities for a source and a drain on a surface of the semiconductor substrate.  
   
   
       34 . The method of  claim 29 , wherein forming the junction layer includes depositing a silicon layer having doped impurities for a source and a drain on a surface of the semiconductor substrate.  
   
   
       35 . The method of  claim 29 , wherein forming the source and the drain regions and forming of the channel layer includes: 
 forming a mask pattern for defining a gap between source and drain regions on the junction layer reserved for a channel layer;    exposing the semiconductor substrate by performing an anisotrophic etching on the junction layer in a shape of the mask pattern; and    forming a channel layer by epitaxially growing the semiconductor substrate exposed in the gap between the source and drain regions.    
   
   
       36 . The method of  claim 35 , further comprising: 
 forming a high mobility material on a surface of the channel layer after the channel layer has been formed by epitaxially growing the exposed semiconductor substrate.    
   
   
       37 . The method of  claim 36 , wherein the high mobility material is a layer or stacked structure selected from the group consisting of C, Si, Ge and combinations thereof.  
   
   
       38 . The method of  claim 36 , wherein the high mobility material is formed by an epitaxial growth process.  
   
   
       39 . The method of  claim 29 , further comprising: 
 forming a gate oxide layer after forming the channel layer but prior to forming the gate electrode.    
   
   
       40 . The method of  claim 39 , wherein the forming of the gate electrode includes: 
 forming mask patterns on the gate oxide layer so as to expose a space between the mask patterns that is reserved for a gate electrode;    depositing gate electrode material to fill the space;    planarizing the gate electrode material to expose a surface of the mask pattern; and    removing the mask pattern to realize the gate electrode.    
   
   
       41 . The method of  claim 29 , further comprising: 
 forming a corresponding spacer on corresponding sidewalls of the gate electrode after forming the gate electrode; and    forming a silicide layer on the gate electrode, source region and drain region.    
   
   
       42 . The method of  claim 41 , further comprising: 
 removing the isolation film to a given depth so as to expose sidewalls of the source and drain regions after forming the spacers are formed but before forming the silicide layer.    
   
   
       43 . The method of  claim 29 , further comprising: 
 removing the isolation film to a given depth so as to expose sidewalls of the channel layer after forming the channel layer but before forming the gate electrode.    
   
   
       44 . The method of  claim 29 , further comprising: 
 forming a storage node on the channel layer after forming the channel layer but before forming the gate electrode.    
   
   
       45 . A method for manufacturing a field effect transistor (FET), comprising: 
 forming a channel layer on a semiconductor substrate;    forming a gate electrode on the channel layer; forming a spacer on each corresponding sidewall of the gate electrode;    defining regions reserved for a source region and a drain region in the channel layer; and    forming an impurity-containing epitaxial layer in the defined regions to form the source and drain regions.    
   
   
       46 . The method of  claim 45 , wherein defining regions further includes anisotrophically etching the channel layer in a shape of the gate electrode and spacers to form the defined regions reserved for source and drain regions.  
   
   
       47 . The method of  claim 45 , wherein forming the channel layer includes: 
 implanting impurities into a surface of the semiconductor substrate; and    activating the impurities.    
   
   
       48 . The method of  claim 45 , wherein forming the channel layer includes: 
 growing an epitaxial layer on a surface of the semiconductor substrate; and    doping impurities into the epitaxial layer.    
   
   
       49 . The method of  claim 45 , wherein forming of channel layer includes growing an epitaxial layer with doped impurities therein on a surface of the semiconductor substrate.  
   
   
       50 . The method of  claim 45 , wherein forming the channel layer includes depositing a silicon layer having doped impurities therein on a surface of the semiconductor substrate.  
   
   
       51 . The method of  claim 45 , wherein forming the gate electrode includes: 
 forming a gate oxide layer on the channel layer;    depositing gate electrode material on the gate oxide layer;    forming a hard mask layer on the gate electrode material;    forming a photoresist pattern on the hard mask layer so as to define a gate electrode;    patterning the hard mask layer and gate electrode material in a shape of the photoresist pattern; and    removing the photoresist pattern.    
   
   
       52 . The method of  claim 51 , wherein forming the spacers includes oxidizing sidewalls of the gate electrode to a given oxide thickness.  
   
   
       53 . The method of  claim 51 , wherein defining regions for the source and drain regions further includes exposing the semiconductor substrate by etching the gate oxide layer and the channel layer using the gate electrode and spacers as a mask.  
   
   
       54 . The method of  claim 53 , wherein forming the source and drain regions includes performing a selective epitaxial growth (SEG) process on the exposed semiconductor substrate to grow the source and drain regions to a given height.  
   
   
       55 . The method of  claim 45 , further comprising: 
 forming a high mobility material on the channel layer after forming the channel but before forming the gate electrode.    
   
   
       56 . The method of  claim 55 , wherein the high mobility material is a layer or stacked structure selected from the group consisting of C, Si, Ge and combinations thereof.  
   
   
       57 . The method of  claim 55 , wherein forming the high mobility material includes forming the high mobility material by an epitaxial growth process.  
   
   
       58 . The method of  claim 45 , further comprising: 
 forming a gate oxide layer after forming the channel layer but before forming the gate electrode.    
   
   
       59 . The method of  claim 45 , further comprising: 
 forming a storage node after forming the channel layer but before forming the gate electrode.    
   
   
       60 . The method of  claim 45 , further comprising: 
 forming an isolation film on a given portion of the semiconductor substrate after forming the channel layer but before forming the gate electrode,    wherein forming the isolation film and forming the gate electrode further includes:    forming a mask pattern on the channel layer so as to expose a device isolation region;    forming the isolation film on the exposed device isolation region;    forming a resist pattern on the mask pattern so as to expose a space reserved for the gate electrode;    etching the mask pattern and isolation film to a given depth in a shape of the resist pattern;    removing the resist pattern;    depositing a gate electrode material in the exposed space;    planarizing the gate electrode material to expose a surface of the mask pattern, so as to realize the gate electrode; and    removing the mask pattern.    
   
   
       61 . The method of  claim 60 , wherein the isolation film is etched to expose side portions of the channel layer.