Method for forming a metal extrusion free via

Abstract

A process whereby elimination of metal extrusion through the via-barrier layer into the base of etched via holes is accomplished by controlling the process temperature of the via-barrier deposition to less than 400° C., and preferably to about 380° C. By eliminating the cause of metal extrusions, i.e., excessive thermally induced stresses on the metal confined biaxially by the dielectric via walls, the resulting defect-free vias are independent of the barrier thickness. The method is applicable to different metal stacks, and in turn, yield and reliability of the device is significantly enhanced.

What is claimed is:  
     
         1 - A method for making a multilevel integrated circuit device without formation of metal extrusions into a via including the steps of: 
 providing a semiconductor substrate having a dielectric layer,    depositing a metal stack, patterning and etching to form interconnection lines,    depositing one or more dielectric layers, patterning and etching the dielectric to form a via hole to contact an interconnection line,    depositing a seed layer and a via-barrier layer at a controlled temperature, low enough to substantially eliminate stress on the metal interconnection line, and filling the via hole with a metal plug.    
     
     
         2 - A process as in  claim 1  wherein said temperature of via barrier deposition is controlled to between 380° C. and 390° C.  
     
     
         3 - A process as in  claim 1  wherein said metal stack comprises a conductive layer of an aluminum alloy sandwiched between layers of titanium, and titanium nitride in various combinations thereof.  
     
     
         4 - A process as in  claim 1  wherein said metal stack includes reacted titanium aluminide.  
     
     
         5 - A process as in  claim 1  wherein the dielectric comprises a silicon dioxide, HDP, TEOS or other conformal dielectric coating.  
     
     
         6 - A process as in  claim 1  wherein said via-barrier is a CVD deposited TiN.  
     
     
         7 - A process as in  claim 1  wherein the seed layer is Ti.  
     
     
         8 - A process as in  claim 1  wherein said metal plug is CVD deposited tungsten.  
     
     
         9 - A process as in  claim 1  which further includes an antireflective coating on said interconnection lines conductor.  
     
     
         10 - A process as in  claim 8  wherein said antireflective coating comprises TiN.  
     
     
         11 - A process as in  claim 8  wherein said antireflective coating comprises silicon oxynitride.  
     
     
         12 - An integrated circuit device having a multi-level metallization structure thereon made using the process of  claim 1.