Method for manufacturing a scalable high frequency integrated circuit package

Abstract

A method and implementing system are described in which a tri-plate chip carrier is effective to significantly reduce electromagnetic signal radiation and provide enhanced noise immunity. The tri-plate structure includes a ground layer, a middle signal conducting layer upon which an integrated circuit is mounted, and a top reference potential layer. The middle layer includes groups of printed circuit conductors extending from the chip to the outer edges of the carrier. The top layer is arranged to have separate electrically isolated conducting areas for VDD and ground reference potential connections. The conducting areas are arranged such that each group of signal conductors in the middle signal layer has a ground potential area above it and a ground potential area below it to provide enhanced signal isolation and reduced electromagnetic radiation.

What is claimed is:  
     
         1 . An integrated circuit package comprising: 
 a signal substrate layer arranged for having an integrated circuit mounted thereon;    at least one group of signal conductors on said signal substrate layer arranged to be connected between terminals of said integrated circuit and at least one edge of said signal substrate layer;    a first outer substrate layer positioned on a first side of said signal substrate layer; and    a second outer substrate layer positioned on a second side of said signal substrate layer, said first and second outer substrate layers being arranged to have first areas of conducting surfaces thereon connected to a first potential level, said first areas of conducting surfaces being positioned to extend with said group of said signal conductors on at least two sides of said group of said signal conductors.    
     
     
         2 . The integrated circuit package as set forth in  claim 1  wherein said first potential level is ground potential.  
     
     
         3 . The integrated circuit package as set forth in  claim 1  and further including: 
 second areas of conducting surfaces positioned on said first outer substrate layer, said second areas of conducting surface being arranged for connection to a second potential level, said second potential level being different from said first potential level.  
 
     
     
         4 . The integrated circuit package as set forth in  claim 1  wherein said second potential level is a power supply potential.  
     
     
         5 . The integrated circuit package as set forth in  claim 1  wherein said first areas of conducting surfaces are arranged symmetrically on said first outer substrate layer.  
     
     
         6 . The integrated circuit package as set forth in  claim 1  wherein said first areas of conducting surfaces comprise electrically isolated areas of conductive material on said first outer substrate layer, and said first areas of conducting surfaces are connected to conducting areas on said second outer substrate layer through vias passing through said signal substrate layer.  
     
     
         7 . The integrated circuit package as set forth in  claim 1  wherein said one group of signal conductors is arranged between said integrated circuit and only one side of said signal substrate layer.  
     
     
         8 . The integrated circuit package as set forth in  claim 1  wherein said one group of signal conductors is arranged between said integrated circuit and only two sides of said signal substrate layer.  
     
     
         9 . The integrated circuit package as set forth in  claim 1  wherein said one group of signal conductors is arranged between said integrated circuit and all sides of said signal substrate layer.  
     
     
         10 . The integrated circuit package as set forth in  claim 3  and further including at least one de-coupling capacitor connected between one of said first areas of conducting surface on said first outer substrate layer and at least one of said second areas of conducting surface on said second outer substrate layer.  
     
     
         11 . The integrated circuit package as set forth in  claim 10  wherein said first areas of conducting surfaces are connected to first areas of conducting surfaces on said second outer substrate layer through vias passing through said signal substrate layer.  
     
     
         12 . A method for packaging groups of printed signal conductors extending from an integrated circuit mounted on a signal substrate layer to at least one edge of said signal substrate layer, said method comprising: 
 providing a signal substrate layer arranged for having an integrated circuit mounted thereon;    positioning at least one group of signal conductors on said signal substrate layer arranged to be connected between terminals of said integrated circuit and at least one edge of said signal substrate layer;    positioning a first outer substrate layer on a first side of said signal substrate layer; and    positioning a second outer substrate layer on a second side of said signal substrate layer, said first and second outer substrate layers being arranged to have first areas of conducting surfaces thereon connected to a first potential level, said first areas of conducting surfaces being positioned to be extend with said group of said signal conductors on at least two sides of said group of said signal conductors.    
     
     
         13 . The method as set forth in  claim 12  wherein said first potential level is ground potential.  
     
     
         14 . The method as set forth in  claim 12  and further including: 
 providing second areas of conducting surfaces positioned on said first outer substrate layer, said second areas of conducting surface being arranged for connection to a second potential level, said second potential level being different from said first potential level.  
 
     
     
         15 . The method as set forth in  claim 12  wherein said second potential level is a power supply potential.  
     
     
         16 . The method as set forth in  claim 12  and further including arranging said first areas of conducting surfaces symmetrically on said first outer substrate layer.  
     
     
         17 . The method as set forth in  claim 12  wherein said first areas of conducting surfaces comprise electrically isolated areas of conductive material on said first outer substrate layer, said method further including connecting said first areas of conducting surfaces to conducting areas on said second outer substrate layer through vias passing through said signal substrate layer.  
     
     
         18 . The method as set forth in  claim 12  wherein said method further includes arranging said one group of signal conductors between said integrated circuit and only one side of said signal substrate layer.  
     
     
         19 . The method as set forth in  claim 12  wherein said method further includes arranging said signal conductors between said integrated circuit and only two sides of said signal substrate layer.  
     
     
         20 . The method as set forth in  claim 12  wherein said method further includes arranging said signal conductors between said integrated circuit and all sides of said signal substrate layer.  
     
     
         21 . The method as set forth in  claim 14  and further including connecting at least one de-coupling capacitor between one of said first areas of conducting surface on said first outer substrate layer and at least one of said second areas of conducting surface on said second outer substrate layer.  
     
     
         22 . The method as set forth in  claim 21  and further including connecting said first areas of conducting surfaces to first areas of conducting surfaces on said second outer substrate layer through vias passing through said signal substrate layer.