Nonvolatile floating-gate memory devices, and process of fabrication

Abstract

A process of fabricating a floating-gate memory device, the process including the steps of: forming a stack of superimposed layers including a floating gate region, a dielectric region, and a control gate region; and forming an insulating layer of oxynitride to the side of the floating gate region to completely seal the floating gate region outwards and improve the retention characteristics of the memory device. The insulating layer is formed during reoxidation of the sides of the floating gate region, after self-align etching the stack of layers and implanting the source/drain of the cell.

1 . A memory device comprising: 
 a floating gate region having sidewalls;    a dielectric region over said floating gate region;    a control gate region over said dielectric region; and    first oxynitride insulating layers on the sidewalls of said floating gate region.    
     
     
         2 . The memory device of  claim 1 , further comprising second oxynitride insulating layers on sidewalls of said control gate region.  
     
     
         3 . The memory device of  claim 1 , further comprising: 
 a substrate of semiconductor material; and    an insulating layer positioned on the substrate and directly below the floating gate region.    
     
     
         4 . The memory device of  claim 3 , further comprising a source region and a drain region formed in the substrate in areas lateral of a central area below the floating gate region.  
     
     
         5 . The memory device of  claim 1  wherein the floating gate, dielectric, and control gate regions are part of a memory transistor, the memory device further comprising a selection transistor positioned laterally adjacent to the memory transistor, the selection transistor including a control gate region with sidewalls, and second oxynitride insulating layers on the sidewalls of said control gate region of the selection transistor.  
     
     
         6 . The memory device of  claim 5 , further comprising: 
 a substrate of semiconductor material; and    an insulating layer positioned on the substrate and directly below the floating gate region and the control gate region of the selection transistor.    
     
     
         7 . The memory device of  claim 6 , further comprising first, second, and third doped regions formed in the substrate, the first doped region being positioned laterally adjacent to a first end of the floating gate region, the second doped region being positioned laterally adjacent to a second end of the floating gate region and a first end of the control gate region of the selection transistor, and the third doped region being positioned laterally adjacent to a second end of the control gate region of the selection transistor, the second doped region being shared by the memory and selection transistors.  
     
     
         8 . The memory device of  claim 1  wherein the control gate region includes a polysilicon layer and a silicide layer formed on the polysilicon layer.  
     
     
         9 . A floating-gate memory device, comprising: 
 an insulating layer on a semiconductor substrate;    a first polysilicon layer positioned over said insulating layer;    a dielectric material layer positioned over said first polysilicon layer;    a second polysilicon layer positioned over said dielectric layer, wherein the first and second polysilicon layers and the dielectric layer are defined to form a gate stack; and    first oxynitride sidewalls positioned on lateral walls of said second polysilicon layer.    
     
     
         10 . The memory device of  claim 9 , further comprising second oxynitride insulating layers on sidewalls of said first polysilicon layer.  
     
     
         11 . The memory device of  claim 9 , further comprising: 
 a substrate of semiconductor material; and    an insulating layer positioned on the substrate and directly below the floating gate region.    
     
     
         12 . The memory device of  claim 9 , further comprising a source region and a drain region formed in the substrate in areas lateral of a central area below the gate stack.  
     
     
         13 . The memory device of  claim 9  wherein the gate stack is part of a memory transistor, the memory device further comprising a selection transistor positioned laterally adjacent to the memory transistor, the selection transistor including a control gate region with lateral walls, and second oxynitride sidewalls on the lateral walls of said control gate region of the selection transistor.  
     
     
         14 . The memory device of  claim 13 , further comprising first, second, and third doped regions formed in the substrate, the first doped region being positioned laterally adjacent to a first end of the gate stack, the second doped region being positioned laterally adjacent to a second end of the gate stack and a first end of the control gate region of the selection transistor, and the third doped region being positioned laterally adjacent to a second end of the control gate region of the selection transistor, the second doped region being shared by the memory and selection transistors.  
     
     
         15 . The memory device of  claim 9 , further comprising a silicide layer formed on the second polysilicon layer.