Polysilicon thin film transistor with a self-aligned LDD structure

Abstract

A polysilicon thin film transistor (poly-Si TFT) with a self-aligned lightly doped drain (LDD) structure has a transparent insulating substrate; a buffering layer formed on the transparent insulating substrate; a polysilicon layer formed on the buffering layer and having a channel region, an LDD structure surrounding the channel region, and a source/drain region surrounding the LDD structure; a gate insulating layer formed on the polysilicon layer; a gate layer formed on the gate insulating layer and positioned over the channel region; an insulating spacer formed on the sidewall of the gate layer and positioned over the LDD structure; and a sub-gate layer formed on the insulating spacer.

What is claimed is:  
     
         1 . A polysilicon thin film transistor with a self-aligned lightly doped drain (LDD) structure, comprising: 
 a transparent insulating substrate;    a buffering layer formed on the transparent insulating substrate;    a polysilicon layer formed on the buffering layer and having a channel region, an LDD structure surrounding the channel region, and a source/drain region surrounding the LDD structure;    a gate insulating layer formed on the polysilicon layer;    a gate layer formed on the gate insulating layer and positioned over the channel region;    an insulating spacer formed on the sidewall of the gate layer and positioned over the LDD structure; and    a sub-gate layer formed on the insulating spacer.    
     
     
         2 . The polysilicon thin film transistor according to  claim 1 , wherein the transparent insulating layer is of glass materials.  
     
     
         3 . The thin film transistor according to  claim 1 , wherein the doped concentration of the LDD structure is smaller than the doped concentration of the source/drain region.  
     
     
         4 . The thin film transistor according to  claim 1 , wherein the combination of the gate layer and the insulating spacer presents a rectangular profile.  
     
     
         5 . The polysilicon thin film transistor according to  claim 1 , wherein the gate layer is of conductive materials.  
     
     
         6 . The polysilicon thin film transistor according to  claim 1 , wherein the insulating spacer is silicon nitride or silicon oxide.  
     
     
         7 . The polysilicon thin film transistor according to  claim 1 , wherein the sub-gate layer is selected from the group consisting of amorphous silicon, polysilicon and metallic materials.  
     
     
         8 . A method of forming a polysilicon thin film transistor with a self-aligned lightly doped drain (LDD) structure, comprising steps of: 
 providing a transparent insulating substrate, which has a polysilicon layer, a gate insulating layer formed on the polysilicon layer, and a gate layer patterned on the gate insulating layer;    performing a first ion implantation process to form a lightly doped region on the polysilicon layer surrounding the gate layer;    forming an insulating layer and a barrier layer sequentially on the entire surface of the substrate;    removing parts of the barrier layer, wherein the remaining part of the barrier layer is positioned over the sidewall of the gate layer;    removing the insulating layer which is not covered by the remaining part of the barrier layer, wherein the remaining part of the insulating layer is positioned on the sidewall of the gate layer; and    performing a second ion implantation process to form a heavily doped region on the lightly doped region which is not covered by the remaining parts of the insulating layer and the barrier layer.    
     
     
         9 . The method according to  claim 8 , further comprising a step of: completely removing the remaining part of the barrier layer.  
     
     
         10 . The method according to  claim 8 , wherein the transparent insulating substrate is glass.  
     
     
         11 . The method according to  claim 8 , wherein the combination of the gate layer and the remaining part of the insulating layer presents a rectangular profile.  
     
     
         12 . The method according to  claim 8 , wherein the gate layer is of conductive materials.  
     
     
         13 . The method according to  claim 8 , wherein the insulating layer is silicon nitride or silicon oxide.  
     
     
         14 . The method according to  claim 8 , wherein the barrier layer is silicon nitride.  
     
     
         15 . The method according to  claim 8 , wherein the barrier layer is amorphous silicon or polysilicon.  
     
     
         16 . The method according to  claim 8 , wherein the barrier layer is of conductive materials.  
     
     
         17 . The method according to  claim 8 , wherein the step of removing parts of the barrier layer is formed by dry etching.  
     
     
         18 . The method according to  claim 8 , wherein the step of removing the insulating layer covered by the remaining part of the barrier layer is formed by wet etching.