Chip scale package and manufacturing method thereof

Abstract

A chip scale package mainly comprises two elastomer pads respectively interposed between a substrate and a semiconductor chip. Each of the elastomer pads is respectively situated on the flank of a slot centrally defined in the substrate, and keeps a predetermined distance from the slot. The semiconductor chip is attached onto the upper surface of the substrate through the two elastomer pads wherein bonding pads formed on the semiconductor chip are exposed from the slot of the substrate. The upper surface of the substrate is provided with a plurality of solder pads and leads. Each of the leads has one end electrically connected to a corresponding solder pad, and the other end electrically connected to a corresponding bonding pad of the semiconductor chip. The substrate has a plurality of through-holes formed corresponding to the solder pads such that each solder pad has a portion exposed within the through-hole for mounting a solder ball. The chip scale package is electrically connected to outside through the solder balls. The slot of the substrate and the periphery of the semiconductor chip are sealed by an integrally formed package body. The present invention is characterized in that the encapsulation process of the chip scale package is carried out by a single step of dispensing and curing, so as to increase UPH (unit per hour) thereby shortening encapsulation cycle time. Moreover, the occurrence of flash on the substrate surface around the slot during encapsulation can be reduced, thereby assuring the solder joint reliability of the solder pads.

What is claimed is:  
     
         1 . A chip scale package comprising: 
 a substrate having a upper surface, a lower surface, and a slot defined therein, the substrate being provided with a plurality of solder pads on the upper surface thereof, the substrate having a plurality of through-holes corresponding to the solder pads;    a semiconductor chip having a plurality of bonding pads centrally formed thereon, the semiconductor chip being mounted to the upper surface of the substrate in a manner that the bonding pads thereof are exposed from the slot of the substrate;    a plurality of leads disposed within the slot of the substrate, each of the leads having one end electrically connected to the corresponding solder pad and the other end electrically connected to the corresponding bonding pad;    two elastomer pads respectively interposed between the substrate and the semiconductor chip, the two elastomer pads flanking the slot of the substrate and keeping a predetermining distance from the slot;    a package body having a first portion formed on the upper surface of the substrate around the chip and a second portion formed within the slot of the substrate, wherein the two portions are formed substantially at the same time.    
     
     
         2 . The chip scale package as claimed in  claim 1 , wherein the first portion of the package body is formed by dispensing encapsulant onto the upper surface of the substrate around the chip, and the encapsulant fills the slot of the substrate via capillary action to form the second portion of the package body substantially at the same time.  
     
     
         3 . The chip scale package as claimed in  claim 1 , further comprising a plurality of solder balls mounted on the solder pads of the substrate for external electrical connection.  
     
     
         4 . A substrate structure for use in forming a chip scale package, wherein the substrate structure comprising: 
 a substrate having a upper surface adapted for receiving a semiconductor chip, a lower surface, and a slot defined therein:    a plurality of solder pads on the upper surface of the substrate wherein the substrate has a plurality of through-holes corresponding to the solder pads;    a plurality of leads disposed within the slot of the substrate, each of the leads has at least one end electrically connected to corresponding solder pad; and    two elastomer pads on the upper surface of the substrate, the two elastomer pads flanking the slot of the substrate and having a predetermining distance from the slot.    
     
     
         5 . The substrate structure as claimed in  claim 4 , wherein the substrate is one of a plurality of substrates formed in a strip configuration for use in forming a plurality of substrate-based semiconductor chip package.  
     
     
         6 . A method of making a chip scale package comprising the steps of: 
 providing a substrate having a upper surface, a lower surface, and a slot defined therein, the substrate being provided with a plurality of solder pads on the upper surface thereof and a plurality of leads within the slot, wherein the substrate has a plurality of through-holes corresponding to the solder pads, and each of the leads has at least one end electrically connected to corresponding solder pad;    attaching two elastomer pads respectively onto the upper surface of the substrate in a manner that the two elastomer pads flank the slot of the substrate and keep a predetermining distance from the slot;    providing a semiconductor chip having a plurality of bonding pads centrally formed thereon;    attaching the semiconductor chip onto the upper surface of the substrate in a manner that the bonding pads thereof are exposed from the slot of the substrate;    electrically coupling the leads of the substrate and the bonding pads of the semiconductor chip in a manner that the other end of each of the leads is electrically connected to corresponding bonding pad; and    forming a package body having a first portion on the upper surface of the substrate around the chip and a second portion within the slot of the substrate, wherein the two portions are formed substantially at the same time.    
     
     
         7 . The method as claimed in  claim 6 , wherein the first portion of the package body is formed by dispensing encapsulant onto the upper surface of the substrate around the chip, and the encapsulant fills the slot of the substrate via capillary action so as to form the second portion of the package body substantially at the same time.  
     
     
         8 . The method as claimed in  claim 6 , wherein the substrate is one of a plurality of subtrates formed in a strip configuration for use in forming a plurality of subtrate-based semiconductor chip package.  
     
     
         9 . The method as claimed in  claim 6 , further a step of mounting a plurality of solder balls to the solder pads of the substrate for external electrical connection.