Inventor · disambiguated record
Walter Kleemeier
Also filed as: KLEEMEIER WALTER
15 granted patents·1 pending application·112 citations·filing 2009–2020
92Inventor score
Top patents by PatentIndex Score
16 records- 0195US9209305B1Backside source-drain contact for integrated circuit transistor devices and method of making sameST MICROELECTRONICS INC·Filed 2014·Granted Dec 8, 2015·21 cites·33 claims
- 0293US9337087B1Multilayer structure in an integrated circuit for damage prevention and detection and methods of creating the sameST MICROELECTRONICS INC·Filed 2014·Granted May 10, 2016·13 cites·16 claims
- 0393US9240454B1Integrated circuit including a liner silicide with low contact resistanceST MICROELECTRONICS INC·Filed 2014·Granted Jan 19, 2016·14 cites·24 claims
- 0493US8476765B2Copper interconnect structure having a graphene capZHANG JOHN HONGGUANG·Filed 2010·Granted Jul 2, 2013·24 cites·25 claims
- 0592US9543397B2Backside source-drain contact for integrated circuit transistor devices and method of making sameST MICROELECTRONICS INC·Filed 2015·Granted Jan 10, 2017·8 cites·23 claims
- 0691US8569899B2Device and method for alignment of vertically stacked wafers and dieZHANG JOHN H·Filed 2009·Granted Oct 29, 2013·14 cites·17 claims
- 0786US8987780B2Graphene capped HEMT deviceST MICROELECTRONICS INC·Filed 2013·Granted Mar 24, 2015·8 cites·10 claims
- 0883US9646939B2Multilayer structure in an integrated circuit for damage prevention and detection and methods of creating the sameIBM·Filed 2016·Granted May 9, 2017·3 cites·20 claims
- 0982US8900990B2System and method of combining damascenes and subtract metal etch for advanced back end of line interconnectionsST MICROELECTRONICS INC·Filed 2012·Granted Dec 2, 2014·6 cites·11 claims
- 1071US11205621B2Device and method for alignment of vertically stacked wafers and dieST MICROELECTRONICS INC·Filed 2020·Granted Dec 21, 2021·0 cites·12 claims
- 1169US9324660B2Device and method for alignment of vertically stacked wafers and dieST MICROELECTRONICS INC·Filed 2013·Granted Apr 26, 2016·1 cites·13 claims
- 1260US10615125B2Device and method for alignment of vertically stacked wafers and dieST MICROELECTRONICS INC·Filed 2017·Granted Apr 7, 2020·0 cites·12 claims
- 1357US9870999B2Device and method for alignment of vertically stacked wafers and dieST MICROELECTRONICS INC·Filed 2015·Granted Jan 16, 2018·0 cites·23 claims
- 1451US9633909B2Process for integrated circuit fabrication including a liner silicide with low contact resistanceST MICROELECTRONICS INC·Filed 2015·Granted Apr 25, 2017·0 cites·42 claims
- 1550US8560111B2Method of determining pressure to apply to wafers during a CMPZHANG JOHN H·Filed 2009·Granted Oct 15, 2013·0 cites·16 claims
- 1633US2016300857A1Junctionless finfet device and method for manufactureST MICROELECTRONICS INC·Filed 2015·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →