Inventor · disambiguated record
Takeo Nakada
Also filed as: NAKADA TAKEO
9 granted patents·3 pending applications·254 citations·filing 1990–2015
88Inventor score
Top patents by PatentIndex Score
12 records- 0188US5222229AMultiprocessor system having synchronization control mechanismIBM·Filed 1990·Granted Jun 22, 1993·167 cites·10 claims
- 0281US10237058B2Identification of artificail object and artifical object used thereinIBM·Filed 2015·Granted Mar 19, 2019·4 cites·44 claims
- 0364US5265215AMultiprocessor system and interrupt arbiter thereofIBM·Filed 1992·Granted Nov 23, 1993·51 cites·1 claims
- 0462US8683142B2Technique and apparatus for identifying cache segments for caching data to be written to main memoryHARADA NOBUYUKI·Filed 2012·Granted Mar 25, 2014·1 cites·9 claims
- 0561US8266385B2Technique and apparatus for identifying cache segments for caching data to be written to main memoryHARADA NOBUYUKI·Filed 2008·Granted Sep 11, 2012·2 cites·15 claims
- 0655US7315964B2Digital signal measuring apparatus and traffic observing methodIBM·Filed 2003·Granted Jan 1, 2008·3 cites·16 claims
- 0750US2008005622A1Digital Signal Measuring Apparatus and Traffic Observing MethodIBM·Filed 2007·Application pending·0 cites
- 0845US2009019235A1Apparatus and method for caching data in a computer memoryHARADA NOBUYUKI·Filed 2008·Application pending·0 cites
- 0944US8112589B2System for caching data from a main memory with a plurality of cache statesHARADA NOBUYUKI·Filed 2008·Granted Feb 7, 2012·0 cites·13 claims
- 1041US6049852APreserving cache consistency in a computer system having a plurality of memories with overlapping address rangesIBM·Filed 1995·Granted Apr 11, 2000·18 cites·1 claims
- 1139US2008320236A1System having cache snoop interface independent of system bus interfaceUEDA MAKOTO·Filed 2007·Application pending·0 cites
- 1235US5913225ACache flush mechanism for a secondary cache memoryIBM·Filed 1995·Granted Jun 15, 1999·8 cites·9 claims
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