Inventor

GOPAL VINODH

US323 patents

⚠️ This page may combine multiple inventors who share the name “GOPAL VINODH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GOPAL VINODH

INTEL CORP

Technologies for performing speculative decompression

Architecture and instruction set for implementing advanced encryption standard (AES)

Systems and methods for performing matrix compress and decompress instructions

Technologies for deterministic constant-time data compression

Technologies for performing speculative decompression

Technologies for flexibly compressing and decompressing data

Method and apparatus to process 4-operand SIMD integer multiply-accumulate instruction

Methods and apparatus to parallelize data decompression

Technologies for efficiently compressing data with multiple hash tables

Technologies for efficiently compressing data with run detection

Technologies for heuristic huffman code generation

Technologies for performing low-latency decompression with tree caching

Technologies for high-performance single-stream LZ77 compression

Method and apparatus for high performance compression and decompression

Method and apparatus for accelerating canonical huffman encoding

Efficient dictionary for lossless compression

Look-ahead hash chain matching for data compression

Techniques for data compression verification

Instructions and logic to provide SIMD SM4 cryptographic block cipher functionality

Supporting data compression using match scoring

Architecture and instruction set for implementing advanced encryption standard (AES)

Instruction and logic to provide SIMD secure hashing round slice functionality

Multiplying two numbers

Hardware accelerator

System and method for cryptography processing units and multiplier

Systems and methods for performing matrix compress and decompress instructions

Systems and methods for performing matrix compress and decompress instructions

Keyed-hash message authentication code processors, methods, systems, and instructions

Hardware accelerators and methods for offload operations

Instruction and logic to provide SIMD secure hashing round slice functionality

Technologies for a high-ratio compression accelerator with heterogeneous history buffers

Architecture and instruction set for implementing advanced encryption standard (AES)

Architecture and instruction set for implementing advanced encryption standard (AES)

SM3 hash function message expansion processors, methods, systems, and instructions

Architecture and instruction set for implementing advanced encryption standard (AES)

Flexible architecture and instruction for advanced encryption standard (AES)

Techniques for parallel data decompression

Instructions and logic to provide SIMD SM4 cryptographic block cipher functionality

Double affine mapped S-box hardware accelerator

Hardware enforced one-way cryptography

Method and apparatus for prefix decoding acceleration

Instruction and logic to provide a secure cipher hash round functionality

GOPAL VINODH

Matrix multiply accumulate instruction

SIMD integer multiply-accumulate instruction for multi-precision arithmetic

Filter for network intrusion and virus detection

Method and apparatus for performing a shift and exclusive or operation in a single instruction

GUERON SHAY

Architecture and instruction set for implementing advanced encryption standard (AES)

Flexible architecture and instruction for advanced encryption standard (AES)

RADHAKRISHNAN SIVAKUMAR

Efficient and scalable cyclic redundancy check circuit using Galois-field arithmetic

FEGHALI WAJDI K

Cryptographic system, method and multiplier