Inventor · disambiguated record
Mauricio J. Serrano
Also filed as: SERRANO MAURICIO · SERRANO MAURICIO J · SERRANO MAURICIO JOSE
46 granted patents·8 pending applications·871 citations·filing 1998–2022
98Inventor score
Top patents by PatentIndex Score
54 records- 0197US9304835B1Optimized system for analytics (graphs and sparse matrices) operationsIBM·Filed 2014·Granted Apr 5, 2016·48 cites·10 claims
- 0294US6973646B1Method for compiling program components in a mixed static and dynamic environmentIBM·Filed 2000·Granted Dec 6, 2005·120 cites·8 claims
- 0393US9400700B2Optimized system for analytics (graphs and sparse matrices) operationsIBM·Filed 2015·Granted Jul 26, 2016·11 cites·9 claims
- 0492US9983878B2Branch prediction using multiple versions of history dataIBM·Filed 2014·Granted May 29, 2018·12 cites·16 claims
- 0592US9778967B2Sophisticated run-time system for graph processingIBM·Filed 2015·Granted Oct 3, 2017·8 cites·20 claims
- 0692US6292938B1Retargeting optimized code by matching tree patterns in directed acyclic graphsIBM·Filed 1998·Granted Sep 18, 2001·212 cites·39 claims
- 0791US7434037B2System for target branch prediction using correlation of local target histories including update inhibition for inefficient entriesIBM·Filed 2006·Granted Oct 7, 2008·23 cites·6 claims
- 0889US10417304B2Dual phase matrix-vector multiplication systemIBM·Filed 2017·Granted Sep 17, 2019·5 cites·20 claims
- 0989US9772890B2Sophisticated run-time system for graph processingIBM·Filed 2014·Granted Sep 26, 2017·10 cites·19 claims
- 1089US6381738B1Method for optimizing creation and destruction of objects in computer programsIBM·Filed 1999·Granted Apr 30, 2002·165 cites·13 claims
- 1188US7793049B2Mechanism for data cache replacement based on region policiesIBM·Filed 2007·Granted Sep 7, 2010·28 cites·18 claims
- 1287US6530079B1Method for optimizing locks in computer programsIBM·Filed 1999·Granted Mar 4, 2003·130 cites·21 claims
- 1386US10078514B2Techniques for dynamic sequential instruction prefetchingIBM·Filed 2016·Granted Sep 18, 2018·4 cites·20 claims
- 1485US8756581B2Adaptive next-executing-cycle trace selection for trace-driven code optimizersCASTANOS JOSE G·Filed 2011·Granted Jun 17, 2014·18 cites·22 claims
- 1585US8756582B2Tracking a programs calling context using a hybrid code signatureSERRANO MAURICIO J·Filed 2011·Granted Jun 17, 2014·10 cites·25 claims
- 1678US8122438B2Computer implemented method and system for accurate, efficient and adaptive calling context profilingCAIN III HAROLD WADE·Filed 2008·Granted Feb 21, 2012·7 cites·14 claims
- 1777US9928158B2Redundant transactions for detection of timing sensitive errorsIBM·Filed 2016·Granted Mar 27, 2018·2 cites·3 claims
- 1875US7900026B2Target branch prediction using a plurality of tablesIBM·Filed 2008·Granted Mar 1, 2011·6 cites·21 claims
- 1973US10379857B2Dynamic sequential instruction prefetchingIBM·Filed 2018·Granted Aug 13, 2019·1 cites·20 claims
- 2072US10795683B2Predicting indirect branches using problem branch filtering and pattern cacheIBM·Filed 2014·Granted Oct 6, 2020·3 cites·8 claims
- 2172US9495164B2Branch prediction using multiple versions of history dataIBM·Filed 2016·Granted Nov 15, 2016·1 cites·1 claims
- 2272US7921260B2Preferred write-mostly data cache replacement policiesIBM·Filed 2007·Granted Apr 5, 2011·5 cites·17 claims
- 2370US9304863B2Transactions for checkpointing and reverse executionIBM·Filed 2013·Granted Apr 5, 2016·2 cites·19 claims
- 2470US9189365B2Hardware-assisted program trace collection with selectable call-signature captureIBM·Filed 2013·Granted Nov 17, 2015·2 cites·12 claims
- 2569US10175987B2Instruction prefetching in a computer processor using a prefetch prediction vectorIBM·Filed 2016·Granted Jan 8, 2019·1 cites·18 claims
- 2669US9483271B2Compressed indirect prediction cachesIBM·Filed 2013·Granted Nov 1, 2016·2 cites·20 claims
- 2769US8621150B2Data placement optimization using data context collected during garbage collectionSERRANO MAURICIO J·Filed 2010·Granted Dec 31, 2013·3 cites·17 claims
- 2867US7818722B2Computer implemented method and system for accurate, efficient and adaptive calling context profilingIBM·Filed 2006·Granted Oct 19, 2010·3 cites·1 claims
- 2966US8489866B2Branch trace history compressionMESTAN BRIAN ROBERT·Filed 2010·Granted Jul 16, 2013·3 cites·17 claims
- 3065US8479184B2General purpose emit for use in value profilingDOING RICHARD WILLIAM·Filed 2010·Granted Jul 2, 2013·2 cites·17 claims
- 3161US10984073B2Dual phase matrix-vector multiplication systemIBM·Filed 2019·Granted Apr 20, 2021·0 cites·20 claims
- 3260US10664279B2Instruction prefetching in a computer processor using a prefetch prediction vectorIBM·Filed 2019·Granted May 26, 2020·0 cites·18 claims
- 3360US7490117B2Dynamic performance monitoring-based approach to memory managementINTEL CORP·Filed 2003·Granted Feb 10, 2009·15 cites·13 claims
- 3458US10713056B2Wide vector execution in single thread mode for an out-of-order processorIBM·Filed 2017·Granted Jul 14, 2020·0 cites·7 claims
- 3558US9904551B2Branch prediction using multiple versions of history dataIBM·Filed 2016·Granted Feb 27, 2018·0 cites·1 claims
- 3658US9898295B2Branch prediction using multiple versions of history dataIBM·Filed 2016·Granted Feb 20, 2018·0 cites·1 claims
- 3757US7389385B2Methods and apparatus to dynamically insert prefetch instructions based on compiler and garbage collector analysisINTEL CORP·Filed 2003·Granted Jun 17, 2008·5 cites·13 claims
- 3856US10705847B2Wide vector execution in single thread mode for an out-of-order processorIBM·Filed 2017·Granted Jul 7, 2020·0 cites·10 claims
- 3955US9459979B2Detection of hardware errors using redundant transactions for system testIBM·Filed 2013·Granted Oct 4, 2016·0 cites·20 claims
- 4055US9251014B2Redundant transactions for detection of timing sensitive errorsIBM·Filed 2013·Granted Feb 2, 2016·0 cites·17 claims
- 4155US7577947B2Methods and apparatus to dynamically insert prefetch instructions based on garbage collector analysis and layout of objectsINTEL CORP·Filed 2003·Granted Aug 18, 2009·4 cites·30 claims
- 4255US2016147536A1Transitioning the Processor Core from Thread to Lane Mode and Enabling Data Transfer Between the Two ModesIBM·Filed 2014·Application pending·0 cites
- 4354US9619356B2Detection of hardware errors using periodically synchronized redundant transactions and comparing results from cores of a multi-core processorIBM·Filed 2015·Granted Apr 11, 2017·0 cites·7 claims
- 4451US2024176584A1Scalable Switch Capacitor Computation Cores for Accurate and Efficient Deep Learning InferenceIBM·Filed 2022·Application pending·0 cites
- 4550US11132228B2SMT processor to create a virtual vector register file for a borrower thread from a number of donated vector register filesIBM·Filed 2018·Granted Sep 28, 2021·0 cites·18 claims
- 4649US9524166B2Tracking long GHV in high performance out-of-order superscalar processorsIBM·Filed 2013·Granted Dec 20, 2016·0 cites·17 claims
- 4749US2013055033A1Hardware-assisted program trace collection with selectable call-signature captureFRAZIER GILES R·Filed 2011·Application pending·0 cites
- 4848US2016147537A1Transitioning the Processor Core from Thread to Lane Mode and Enabling Data Transfer Between the Two ModesIBM·Filed 2015·Application pending·0 cites
- 4944US2005120337A1Memory trace bufferFiled 2003·Application pending·0 cites
- 5043US10558429B2Switching matrix representation for an incremental algorithm computing connected componentsIBM·Filed 2016·Granted Feb 11, 2020·0 cites·20 claims
Showing the top 50 of 54 patent records by PatentIndex Score.
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