Inventor

HAKURA ZIYAD S

US63 patents

⚠️ This page may combine multiple inventors who share the name “HAKURA ZIYAD S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HAKURA ZIYAD S

NVIDIA CORP

Apparatus, system, and method for Z-culling

Method and apparatus to accelerate rendering of shadow effects for computer-generated images

System and method for accelerating a special purpose processor

Primitive re-ordering between world-space and screen-space pipelines with buffer limited processing

Method and apparatus to accelerate rendering of shadows

Apparatus, system, and method for Z-culling

System, apparatus and method for issuing predictions from an inventory to access a memory

Setting downstream render state in an upstream shader

Managing event count reports in a tile-based architecture

Higher accuracy Z-culling in a tile-based architecture

Mid-primitive graphics execution preemption

Order-preserving distributed rasterizer

System, apparatus and method for predicting accesses to a memory

Screen compression

Managing per-tile event count reports in a tile-based architecture

Power efficient attribute handling for tessellation and geometry shaders

Scheduling cache traffic in a tile-based architecture

Hierarchical tiled caching

Caching of adaptively sized cache tiles in a unified L2 cache with surface compression

Technique for storing shared vertices

Data structures for efficient tiled rendering

Two-pass cache tile processing for visibility testing in a tile-based architecture

Managing event count reports in a tile-based architecture

Two-pass cache tile processing for visibility testing in a tile-based architecture

Tiled cache invalidation

Technique for storing shared vertices

On-chip anti-alias resolve in a cache tiling architecture

Barrier commands in a cache tiling architecture

Generating clip state for a batch of vertices

Techniques for managing graphics processing resources in a tile-based architecture

Heuristics for improving performance in a tile based architecture

Techniques for managing graphics processing resources in a tile-based architecture

Heuristics for improving performance in a tile-based architecture

Distributed tiled caching

Techniques for managing graphics processing resources in a tile-based architecture

HAKURA ZIYAD S

Cull before vertex attribute fetch and vertex lighting

Distributed stream output in a parallel processing unit

Calculation of plane equations after determination of Z-buffer visibility

Distributed calculation of plane equations

Distributed vertex attribute fetch

Cull before vertex attribute fetch and vertex lighting

Distributed clip, cull, viewport transform and perspective correction

Vertex attribute buffer for inline immediate attributes and constants

RHOADES JOHNNY S

Distributing primitives to multiple rasterizers

Distributing primitives to multiple rasterizers

Redistribution of generated geometric primitives

MICROSOFT CORP

Parameterized animation compression methods and arrangements

LINDHOLM JOHN ERIK

Generating clip state for a batch of vertices

PURCELL TIMOTHY JOHN

Parallel line stipple computation

MOLNAR STEVEN E

Order-preserving distributed rasterizer