Inventor · disambiguated record
Mani Azimi
Also filed as: AZIMI MANI
12 granted patents·151 citations·filing 1996–2017
91Inventor score
Technology areasG06F
Top patents by PatentIndex Score
12 records- 0186US8990506B2Replacing cache lines in a cache memory based at least in part on cache coherency state informationCHERUKURI NAVEEN·Filed 2009·Granted Mar 24, 2015·17 cites·20 claims
- 0284US9606797B2Compressing execution cycles for divergent execution in a single instruction multiple data (SIMD) processorINTEL CORP·Filed 2012·Granted Mar 28, 2017·12 cites·26 claims
- 0384US9424191B2Scalable coherence for multi-core processorsCHERUKURI NAVEEN·Filed 2012·Granted Aug 23, 2016·9 cites·27 claims
- 0482US9418011B2Region based technique for accurately predicting memory accessesSOARES LIVIO B·Filed 2010·Granted Aug 16, 2016·10 cites·17 claims
- 0579US10048966B2Instruction set for supporting wide scalar pattern matchesINTEL CORP·Filed 2017·Granted Aug 14, 2018·2 cites·18 claims
- 0679US9674114B2Modular decoupled crossbar for on-chip routerPARK DONGKOOK·Filed 2012·Granted Jun 6, 2017·10 cites·18 claims
- 0779US9424031B2Techniques for enabling bit-parallel wide string matching with a SIMD registerINTEL CORP·Filed 2013·Granted Aug 23, 2016·6 cites·25 claims
- 0878US9542186B2Instruction set for supporting wide scalar pattern matchesINTEL CORP·Filed 2015·Granted Jan 10, 2017·2 cites·18 claims
- 0969US6263397B1Mechanism for delivering interrupt messagesINTEL CORP·Filed 1998·Granted Jul 17, 2001·51 cites·36 claims
- 1067US8683136B2Apparatus and method for improving data prefetching efficiency using history based prefetchingCHERUKURI NAVEEN·Filed 2010·Granted Mar 25, 2014·2 cites·27 claims
- 1158US5848279AMechanism for delivering interrupt messagesINTEL CORP·Filed 1996·Granted Dec 8, 1998·30 cites·6 claims
- 1246US9152419B2Instruction set for supporting wide scalar pattern matchesTHANTRY HARIHARAN L·Filed 2012·Granted Oct 6, 2015·0 cites·24 claims
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