Inventor · disambiguated record
Aubrey Deene Ogden
Also filed as: OGDEN AUBREY D · OGDEN AUBREY DEENE
17 granted patents·621 citations·filing 1992–2001
95Inventor score
Top patents by PatentIndex Score
17 records- 0190US6430190B1Method and apparatus for message routing, including a content addressable memoryCISCO TECH IND·Filed 2001·Granted Aug 6, 2002·81 cites·11 claims
- 0289US5764969AMethod and system for enhanced management operation utilizing intermixed user level and supervisory level instructions with partial concept synchronizationIBM·Filed 1995·Granted Jun 9, 1998·168 cites·12 claims
- 0374US6236658B1Method and apparatus for message routing, including a content addressable memoryCISCO TECH IND·Filed 1997·Granted May 22, 2001·80 cites·7 claims
- 0466US5420808ACircuitry and method for reducing power consumption within an electronic circuitIBM·Filed 1993·Granted May 30, 1995·39 cites·42 claims
- 0564US5465373AMethod and system for single cycle dispatch of multiple instructions in a superscalar processor systemIBM·Filed 1993·Granted Nov 7, 1995·46 cites·7 claims
- 0661US5694565AMethod and device for early deallocation of resources during load/store multiple operations to allow simultaneous dispatch/execution of subsequent instructionsIBM·Filed 1995·Granted Dec 2, 1997·34 cites·4 claims
- 0759US5867684AMethod and processor that permit concurrent execution of a store multiple instruction and a dependent instructionIBM·Filed 1997·Granted Feb 2, 1999·30 cites·2 claims
- 0853US5978896AMethod and system for increased instruction dispatch efficiency in a superscalar processor systemIBM·Filed 1994·Granted Nov 2, 1999·26 cites·8 claims
- 0953US5539681ACircuitry and method for reducing power consumption within an electronic circuitIBM·Filed 1996·Granted Jul 23, 1996·21 cites·18 claims
- 1046US5491829AMethod and system for indexing the assignment of intermediate storage buffers in a superscalar processor systemIBM·Filed 1995·Granted Feb 13, 1996·20 cites·6 claims
- 1145US5715420AMethod and system for efficient memory management in a data processing system utilizing a dual mode translation lookaside bufferIBM·Filed 1995·Granted Feb 3, 1998·20 cites·15 claims
- 1242US5898882AMethod and system for enhanced instruction dispatch in a superscalar processor system utilizing independently accessed intermediate storageIBM·Filed 1993·Granted Apr 27, 1999·13 cites·10 claims
- 1342US5764942AMethod and system for selective serialization of instruction processing in a superscalar processor systemIBM·Filed 1996·Granted Jun 9, 1998·14 cites·8 claims
- 1439US5732005ASingle-precision, floating-point register array for floating-point units performing double-precision operations by emulationIBM·Filed 1995·Granted Mar 24, 1998·12 cites·13 claims
- 1534US5758141AMethod and system for selective support of non-architected instructions within a superscaler processor system utilizing a special access bit within a machine state registerIBM·Filed 1995·Granted May 26, 1998·7 cites·8 claims
- 1634US5655141AMethod and system for storing information in a processing systemIBM·Filed 1996·Granted Aug 5, 1997·8 cites·24 claims
- 1724US5341502ADevice for assigning a shared resource in a data processing systemMOTOROLA INC·Filed 1992·Granted Aug 23, 1994·2 cites·6 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →