Inventor

POULTON JOHN W

US115 patents

⚠️ This page may combine multiple inventors who share the name “POULTON JOHN W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

POULTON JOHN W

RAMBUS INC

Communication system with low power, DC-balanced serial link

Wide-range multi-phase clock generator

Phase controlled oscillator circuit with input signal coupler

Maintenance operations in a DRAM

Maintenance operations in a DRAM

Maintenance operations in a DRAM

Signaling system with low-power automatic gain control

Data communications circuit with multi-stage multiplexing

Transition-time control in a high-speed data transmitter

Low power, DC-balanced serial link transmitter

Clock multiplying delay-locked loop for data communications

Signaling interface with phase and framing calibration

Memory controller with transaction-queue-dependent power modes

Memory controller with transaction-queue-monitoring power mode circuitry

Phase controlled oscillator circuit with input signal coupler

Phase controlled oscillator circuit with input signal coupler

Phase controlled oscillator circuit with input signal coupler

Processor controlled interface

Memory IC with data loopback

Memory controller with looped-back calibration data receiver

Forwarding signal supply voltage in data transmission system

Clock-forwarding memory controller with mesochronously-clocked signaling interface

Chip-to-chip signaling link timing calibration

Signaling system with low-power automatic gain control

WARE FREDERICK A

Mesochronous signaling system with multiple power modes

Mesochronous signaling system with clock-stopped low power mode

Maintenance operations in a DRAM

Clock-forwarding low-power signaling system

Mesochronous signaling system with core-clock synchronization

UNIV NORTH CAROLINA

Methods and systems for transmitting and receiving differential signals over a plurality of conductors

Architecture and apparatus for image generation utilizing enhanced memory devices

Architecture and apparatus for image generation

VLSI graphics display image buffer using logic enhanced pixel memory cells

VELIO COMMUNICATIONS INC

Phase controlled oscillator

Low-power low-jitter variable delay timing circuit

Low-power low-jitter variable delay timing circuit

Combined phase comparator and charge pump circuit

ZERBE JARED L

High-speed signaling systems with adaptable pre-emphasis and equalization

High-speed signaling systems with adaptable pre-emphasis and equalization

High-speed signaling systems with adaptable pre-emphasis and equalization

High-speed signaling systems with adaptable pre-emphasis and equalization

POULTON JOHN W

Ground referenced single-ended signaling

Configurable, power supply voltage referenced single-ended signaling with ESD protection

Data-driven charge-pump transmitter for differential signaling

NVIDIA CORP

Ground referenced single-ended signaling

On-package multiprocessor ground-referenced single-ended interconnect

DALLY WILLIAM J

Signaling system with low-power automatic gain control

Clamped bit line read circuit

VELIO COMMUNICAITONS INC

Data communications circuit with multi-stage multiplexing

BEST SCOTT C

Forwarding signal supply voltage in data transmission system