Inventor

ZHANG SHAYAN

CN50 patents

⚠️ This page may combine multiple inventors who share the name “ZHANG SHAYAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ZHANG SHAYAN

FREESCALE SEMICONDUCTOR INC

SRAM with read and write assist

Integrated circuit having a memory with low voltage read/write operation

Integrated circuit having memory with configurable read/write operations and method therefor

Integrated circuit having a memory with low voltage read/write operation

Minimum memory operating voltage technique

Memory with robust data sensing and method for sensing data

Performance based power management of a memory and a data storage system using the memory

Level shifter for change of both high and low voltage

Memory operation testing

Memory system with RAM array and redundant RAM memory cells having a different designed cell circuit topology than cells of non redundant RAM array

Controlled reliability in an integrated circuit

Integrated circuit having an embedded memory and method for testing the memory

Adjustable pipeline in a memory circuit

Method and apparatus for determining feasibility of memory operating condition change using different back bias voltages

Single-supply, single-ended level conversion circuit for an integrated circuit having multiple power supply domains

Data processing system with secure key generation

Low voltage memory device and method thereof

Circuit for testing power supplies in multiple power modes

Integrated circuit memory having dynamically adjustable read margin and method therefor

Memory with read cycle write back

Integrated circuit with selectable power-on reset mode

Memory array with read only cells having multiple states and method of programming thereof

Memory array with RAM and embedded ROM

ZHANG SHAYAN

Integrated circuit memory having assisted access and method therefor

Voltage-based memory size scaling in a data processing system

Methods for testing a memory embedded in an integrated circuit

Recoverable and reconfigurable pipeline structure for state-retention power gating

Method and apparatus for activating system components

Configurable flip-flop

RUSSELL ANDREW C

Multi-port memory having a variable number of used write ports

Memory using multiple supply voltages

Data processing having multiple low power modes and method therefor

HUNTER BRADFORD L

Memory and method for sensing data in a memory using complementary sensing scheme

Memory and method for sensing data in a memory using complementary sensing scheme

RAMARAJU RAVINDRARAJ

Memory voltage regulator with leakage current voltage control

Electronic circuit having shared leakage current reduction circuits

ZHANG WENZHONG

Self-adapting voltage amplifier and battery charger detection

Voltage level shifter

KENKARE PRASHANT U

Integrated circuit having memory repair information storage and method therefor

ZHANG WANGGEN

Low power scan flip-flop cell

WAN GUOPING

System and method for performing scan test

HOEFLER ALEXANDER B

Address fault detection circuit

WANG LING

Reconfigurable circuit and decoder therefor

ZHANG XU

Reconfigurable integrated circuit

XU XIUQIANG

On-chip current test circuit

LIU YIFENG

State retention power gated cell

BAI HAIFENG

Mixed signal IP core prototyping system

XIE MINGQIN

System on chip and control module therefor

SHEN BAIQUAN

Low power SRPG cell

GUO ZIYU

Memory device retention mode based on error information