Inventor · disambiguated record
Stephane Denorme
Also filed as: DENORME STEPHANE · DENORME STÉPHANE
12 granted patents·3 pending applications·10 citations·filing 2010–2025
84Inventor score
Files withST MICROELECTRONICS SA7COMMISSARIAT ENERGIE ATOMIQUE1COMMISSARIAT Á L ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES1CORONEL PHILIPPE1FENOUILLET-BÉRANGER CLAIRE1
Top patents by PatentIndex Score
15 records- 0195US11621051B2Electronic chip memoryST MICROELECTRONICS ROUSSET·Filed 2022·Granted Apr 4, 2023·2 cites·20 claims
- 0283US9881928B2Method for producing one-time-programmable memory cells and corresponding integrated circuitST MICROELECTRONICS SA·Filed 2017·Granted Jan 30, 2018·3 cites·20 claims
- 0379US11250930B2Electronic chip memoryST MICROELECTRONICS SA·Filed 2019·Granted Feb 15, 2022·2 cites·19 claims
- 0479US11164647B2Electronic chip memoryST MICROELECTRONICS SA·Filed 2019·Granted Nov 2, 2021·2 cites·20 claims
- 0558US8314453B2SRAM memory cell with four transistors provided with a counter-electrodeTHOMAS OLIVIER·Filed 2011·Granted Nov 20, 2012·1 cites·15 claims
- 0657US2025287584A1One-time programmable memory cellST MICROELECTRONICS INT NV·Filed 2025·Application pending·0 cites
- 0753US11355503B2Electronic chip memoryST MICROELECTRONICS SA·Filed 2019·Granted Jun 7, 2022·0 cites·20 claims
- 0851US9589968B2Method for producing one-time-programmable memory cells and corresponding integrated circuitST MICROELECTRONICS SA·Filed 2015·Granted Mar 7, 2017·0 cites·21 claims
- 0946US8877600B2Method for manufacturing a hybrid SOI/bulk semiconductor waferST MICROELECTRONICS CROLLES 2·Filed 2013·Granted Nov 4, 2014·0 cites·8 claims
- 1044US9275891B2Process for fabricating an integrated circuit having trench isolations with different depthsCommissariat à l'énergie atomique et aux énergies alternatives·Filed 2013·Granted Mar 1, 2016·0 cites·14 claims
- 1143US8368128B2Compact field effect transistor with counter-electrode and fabrication methodCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2011·Granted Feb 5, 2013·0 cites·12 claims
- 1241US8674443B2Substrate provided with a semi-conducting area associated with two counter-electrodes and device comprising one such substrateCORONEL PHILIPPE·Filed 2011·Granted Mar 18, 2014·0 cites·11 claims
- 1332US8936993B2Hybrid substrate with improved isolation and simplified method for producing a hybrid substrateFENOUILLET-BÉRANGER CLAIRE·Filed 2010·Granted Jan 20, 2015·0 cites·18 claims
- 1432US2017301681A1Configurable romST MICROELECTRONICS SA·Filed 2016·Application pending·0 cites
- 1527US2016307640A1Method and device for programming memory cells of the one-time-programmable typeST MICROELECTRONICS SA·Filed 2015·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →