Inventor · disambiguated record
Sebastian Winkel
Also filed as: WINKEL SEBASTIAN · WINKEL SEBASTIAN C · WINKEL SEBASTIAN CHRISTOPH ALBERT
20 granted patents·11 pending applications·50 citations·filing 2008–2022
91Inventor score
Top patents by PatentIndex Score
31 records- 0190US8762127B2Transitioning from source instruction set architecture (ISA) code to translated code in a partial emulation environmentINTEL CORP·Filed 2013·Granted Jun 24, 2014·13 cites·19 claims
- 0288US10324724B2Hardware apparatuses and methods to fuse instructionsINTEL CORP·Filed 2015·Granted Jun 18, 2019·7 cites·24 claims
- 0388US9274799B1Instruction and logic for scheduling instructionsINTEL CORP·Filed 2014·Granted Mar 1, 2016·11 cites·20 claims
- 0484US9116729B2Handling of binary translated self modifying code and cross modifying codeINTEL CORP·Filed 2012·Granted Aug 25, 2015·10 cites·24 claims
- 0575US10216516B2Fused adjacent memory storesINTEL CORP·Filed 2016·Granted Feb 26, 2019·2 cites·24 claims
- 0667US10055256B2Instruction and logic for scheduling instructionsINTEL CORP·Filed 2016·Granted Aug 21, 2018·1 cites·16 claims
- 0767US9904546B2Instruction and logic for predication and implicit destinationINTEL CORP·Filed 2015·Granted Feb 27, 2018·1 cites·20 claims
- 0863US10877765B2Apparatuses and methods to assign a logical thread to a physical threadINTEL CORP·Filed 2015·Granted Dec 29, 2020·1 cites·24 claims
- 0958US10884735B2Instruction and logic for predication and implicit destinationINTEL CORP·Filed 2018·Granted Jan 5, 2021·0 cites·20 claims
- 1058US8775153B2Transitioning from source instruction set architecture (ISA) code to translated code in a partial emulation environmentWINKEL SEBASTIAN·Filed 2009·Granted Jul 8, 2014·2 cites·24 claims
- 1157US9524170B2Instruction and logic for memory disambiguation in an out-of-order processorTheur Rainer·Filed 2013·Granted Dec 20, 2016·2 cites·20 claims
- 1250US11934809B2Multi-stage automatic compilation for vector computations in applicationsINTEL CORP·Filed 2019·Granted Mar 19, 2024·0 cites·15 claims
- 1350US2024220261A1Instructions and support for conditional load and storeAGRON JASON·Filed 2022·Application pending·0 cites
- 1450US2024220262A1Instructions and support for conditional comparison and testAGRON JASON·Filed 2022·Application pending·0 cites
- 1550US2024220257A1Instructions and support for stack push and popAGRON JASON·Filed 2022·Application pending·0 cites
- 1649US2024220260A1Prefix extensions for extended general purpose registers with optimization features for non-destructive destinations and flags suppressionAGRON JASON·Filed 2022·Application pending·0 cites
- 1747US10540178B2Eliminating redundant stores using a protection designator and a clear designatorINTEL CORP·Filed 2016·Granted Jan 21, 2020·0 cites·13 claims
- 1847US2016179538A1Method and apparatus for implementing and maintaining a stack of predicate values with stack synchronization instructions in an out of order hardware software co-designed processorINTEL CORP·Filed 2014·Application pending·0 cites
- 1946US2016179542A1Instruction and logic to perform a fused single cycle increment-compare-jumpLAI PATRICK P·Filed 2014·Application pending·0 cites
- 2046US2010077145A1Method and system for parallel execution of memory instructions in an in-order processorWINKEL SEBASTIAN C·Filed 2008·Application pending·0 cites
- 2145US12169718B2Systems, methods and apparatus for speculative elimination of load instructionINTEL CORP·Filed 2021·Granted Dec 17, 2024·0 cites·22 claims
- 2245US9996356B2Method and apparatus for recovering from bad store-to-load forwarding in an out-of-order processorINTEL CORP·Filed 2015·Granted Jun 12, 2018·0 cites·14 claims
- 2344US2023315501A1Performance Monitoring Emulation in Translated Branch Instructions in a Binary Translation-Based ProcessorINTEL CORP·Filed 2022·Application pending·0 cites
- 2443US10228956B2Supporting binary translation alias detection in an out-of-order processorINTEL CORP·Filed 2016·Granted Mar 12, 2019·0 cites·20 claims
- 2543US9710389B2Method and apparatus for memory aliasing detection in an out-of-order instruction execution platformINTEL CORP·Filed 2015·Granted Jul 18, 2017·0 cites·24 claims
- 2642US10853078B2Method and apparatus for supporting speculative memory optimizationsINTEL CORP·Filed 2018·Granted Dec 1, 2020·0 cites·20 claims
- 2740US10083033B2Apparatus and method for efficient register allocation and reclamationINTEL CORP·Filed 2015·Granted Sep 25, 2018·0 cites·21 claims
- 2840US2020210193A1Hardware profiler to track instruction sequence information including a blacklisting mechanism and a whitelisting mechanismINTEL CORP·Filed 2018·Application pending·0 cites
- 2939US10346170B2Performing partial register write operations in a processorINTEL CORP·Filed 2015·Granted Jul 9, 2019·0 cites·18 claims
- 3039US2019179766A1Translation table entry prefetching in dynamic binary translation based processorINTEL CORP·Filed 2017·Application pending·0 cites
- 3135US2016283247A1Apparatuses and methods to selectively execute a commit instructionINTEL CORP·Filed 2015·Application pending·0 cites
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