Inventor · disambiguated record
Louis K. Scheffer
Also filed as: SCHEFFER LOUIS · SCHEFFER LOUIS K
35 granted patents·5 pending applications·920 citations·filing 1992–2012
98Inventor score
Top patents by PatentIndex Score
40 records- 0198US7302672B2Method and system for context-specific mask writingCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Nov 27, 2007·71 cites·24 claims
- 0298US7231628B2Method and system for context-specific mask inspectionCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Jun 12, 2007·314 cites·19 claims
- 0392US8020135B2Manufacturing aware design and design aware manufacturing of an integrated circuitCADENCE DESIGN SYSTEMS INC·Filed 2008·Granted Sep 13, 2011·11 cites·34 claims
- 0491US8302061B2Aware manufacturing of an integrated circuitFUJIMURA AKIRA·Filed 2011·Granted Oct 30, 2012·5 cites·19 claims
- 0591US7712064B2Manufacturing aware design of integrated circuit layoutsCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted May 4, 2010·21 cites·36 claims
- 0691US7395516B2Manufacturing aware design and design aware manufacturingCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Jul 1, 2008·10 cites·14 claims
- 0791US7249342B2Method and system for context-specific mask writingCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Jul 24, 2007·37 cites·30 claims
- 0890US5625580AHardware modeling system and method of useSYNOPSYS INC·Filed 1994·Granted Apr 29, 1997·79 cites·20 claims
- 0987US7827519B2Method, system, and computer program product for preparing multiple layers of semiconductor substrates for electronic designsCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Nov 2, 2010·14 cites·25 claims
- 1087US7533359B2Method and system for chip design using physically appropriate component models and extractionCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted May 12, 2009·17 cites·29 claims
- 1186US7784016B2Method and system for context-specific mask writingCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Aug 24, 2010·7 cites·21 claims
- 1285US8407627B2Method and system for context-specific mask inspectionPACK ROBERT C·Filed 2007·Granted Mar 26, 2013·7 cites·36 claims
- 1385US8122392B2Robust design using manufacturability modelsWHITE DAVID·Filed 2008·Granted Feb 21, 2012·12 cites·31 claims
- 1484US8136056B2Method and system for incorporation of patterns and design rule checkingSCHEFFER LOUIS K·Filed 2006·Granted Mar 13, 2012·15 cites·41 claims
- 1581US7721237B2Method, system, and computer program product for timing closure in electronic designsCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted May 18, 2010·11 cites·25 claims
- 1681US7474999B2Method for accounting for process variation in the design of integrated circuitsCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Jan 6, 2009·27 cites·31 claims
- 1780US8713484B2Aware manufacturing of integrated circuitsSCHEFFER LOUIS K·Filed 2010·Granted Apr 29, 2014·5 cites·19 claims
- 1879US7627847B1Method and system for representing manufacturing and lithography information for IC routingCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Dec 1, 2009·7 cites·25 claims
- 1978US8898617B2Robust design using manufacturability modelsWHITE DAVID·Filed 2012·Granted Nov 25, 2014·4 cites·18 claims
- 2077US8769453B2Method, system, and computer program product for preparing multiple layers of semiconductor substrates for electronic designsSCHEFFER LOUIS K·Filed 2010·Granted Jul 1, 2014·4 cites·20 claims
- 2177US7814447B2Supplant design rules in electronic designsCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Oct 12, 2010·8 cites·32 claims
- 2276US7962866B2Method, system, and computer program product for determining three-dimensional feature characteristics in electronic designsCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Jun 14, 2011·7 cites·30 claims
- 2376US6529913B1Database for electronic design automation applicationsCADENCE DESIGN SYSTEMS INC·Filed 2000·Granted Mar 4, 2003·42 cites·51 claims
- 2474US7082588B2Method and apparatus for designing integrated circuit layoutsCADENCE DESIGN SYSTEMS INC·Filed 2004·Granted Jul 25, 2006·18 cites·41 claims
- 2573US7937674B2Method, system, and computer program product for predicting thin film integrity, manufacturability, reliability, and performance in electronic designsCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted May 3, 2011·6 cites·31 claims
- 2673US7546562B1Physical integrated circuit design with uncertain design conditionsCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Jun 9, 2009·6 cites·19 claims
- 2773US5353243AHardware modeling system and method of useSYNOPSYS INC·Filed 1992·Granted Oct 4, 1994·57 cites·111 claims
- 2872US7024638B2Method for creating patterns for producing integrated circuitsCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Apr 4, 2006·21 cites·34 claims
- 2967US7254798B2Method and apparatus for designing integrated circuit layoutsCADENCE DESIGN SYSTEMS INC·Filed 2004·Granted Aug 7, 2007·11 cites·20 claims
- 3067US7207024B2Automatic insertion of clocked elements into an electronic design to improve system performanceCADENCE DESIGN SYTEMS INC·Filed 2003·Granted Apr 17, 2007·15 cites·39 claims
- 3166US6543041B1Method and apparatus for reducing signal integrity and reliability problems in ICS through netlist changes during placementCADENCE DESIGN SYSTEMS INC·Filed 1999·Granted Apr 1, 2003·46 cites·30 claims
- 3265US8103982B2System and method for statistical design rule checkingSCHEFFER LOUIS K·Filed 2006·Granted Jan 24, 2012·3 cites·45 claims
- 3363US8201128B2Method and apparatus for approximating diagonal lines in placementSCHEFFER LOUIS K·Filed 2006·Granted Jun 12, 2012·2 cites·12 claims
- 3454US2009199145A1Method for Accounting for Process Variation in the Design of Integrated CircuitsCADENCE DESIGN SYSTEMS INC·Filed 2009·Application pending·0 cites
- 3551US8117566B2Method and system for representing manufacturing and lithography information for IC routingSCHEFFER LOUIS·Filed 2008·Granted Feb 14, 2012·0 cites·20 claims
- 3651US8103986B2Method and system for representing manufacturing and lithography information for IC routingSCHEFFER LOUIS·Filed 2008·Granted Jan 24, 2012·0 cites·20 claims
- 3750US2012297354A1Method and apparatus for approximating diagonal lines in placementSCHEFFER LOUIS K·Filed 2012·Application pending·0 cites
- 3846US2008162103A1Method, system, and computer program product for concurrent model aided electronic design automationCADENCE DESIGN SYSTEMS INC·Filed 2007·Application pending·0 cites
- 3946US2009164184A1Method and System for Implementing a Complex System or ProcessCADENCE DESIGN SYSTEMS INC·Filed 2008·Application pending·0 cites
- 4044US2006265677A1Method and system for increased accuracy for extraction of electrical parametersCADENCE DESIGN SYSTEMS INC·Filed 2006·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →