Inventor · disambiguated record
Sachidanandan Sambandan
Also filed as: SAMBANDAN SACHIDANANDAN
14 granted patents·1,785 citations·filing 1992–2000
96Inventor score
Top patents by PatentIndex Score
14 records- 0198US6564285B1Synchronous interface for a nonvolatile memoryINTEL CORP·Filed 2000·Granted May 13, 2003·394 cites·18 claims
- 0298US6026465AFlash memory including a mode register for indicating synchronous or asynchronous mode of operationINTEL CORP·Filed 1997·Granted Feb 15, 2000·362 cites·12 claims
- 0397US5696917AMethod and apparatus for performing burst read operations in an asynchronous nonvolatile memoryINTEL CORP·Filed 1994·Granted Dec 9, 1997·204 cites·11 claims
- 0495US6374326B1Multiple bank CAM architecture and method for performing concurrent lookup operationsCISCO TECH IND·Filed 1999·Granted Apr 16, 2002·180 cites·10 claims
- 0595US5317535AGate/source disturb protection for sixteen-bit flash EEPROM memory arraysINTEL CORP·Filed 1992·Granted May 31, 1994·132 cites·9 claims
- 0694US5289412AHigh-speed bias-stabilized current-mirror referencing circuit for non-volatile memoriesINTEL CORP·Filed 1992·Granted Feb 22, 1994·140 cites·5 claims
- 0787US5347484ANonvolatile memory with blocked redundant columns and corresponding content addressable memory setsINTEL CORP·Filed 1994·Granted Sep 13, 1994·68 cites·19 claims
- 0886US5306963AAddress transition detection noise filter in pulse summation circuit for nonvolatile semiconductor memoryINTEL CORP·Filed 1992·Granted Apr 26, 1994·49 cites·18 claims
- 0985US6385688B1Asynchronous interface for a nonvolatile memoryINTEL CORP·Filed 1997·Granted May 7, 2002·89 cites·11 claims
- 1085US5592435APipelined read architecture for memoryINTEL CORP·Filed 1995·Granted Jan 7, 1997·57 cites·6 claims
- 1170US5243575AAddress transition detection to write state machine interface circuit for flash memoryINTEL CORP·Filed 1992·Granted Sep 7, 1993·31 cites·31 claims
- 1267US5926651AOutput buffer with current paths having different current carrying characteristics for providing programmable slew rate and signal strengthINTEL CORP·Filed 1995·Granted Jul 20, 1999·51 cites·20 claims
- 1357US5684752APipelined read architecture for memoryINTEL CORP·Filed 1996·Granted Nov 4, 1997·15 cites·12 claims
- 1450US5418479AMethod and circuitry for generating a safe address transition pulse in a memory deviceINTEL CORP·Filed 1993·Granted May 23, 1995·13 cites·21 claims
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