Inventor · disambiguated record
Brett S. Feero
Also filed as: FEERO BRETT S · FEERO BRETT STANLEY
25 granted patents·2 pending applications·91 citations·filing 2009–2024
94Inventor score
Files withAPPLE INC18ADVANCED RISC MACH LTD3JALAL JAMSHED3CAMPBELL MICHAEL ANDREW1FEERO BRETT STANLEY1
Top patents by PatentIndex Score
27 records- 0195US11886340B1Real-time processing in computer systemsAPPLE INC·Filed 2022·Granted Jan 30, 2024·6 cites·20 claims
- 0291US10223123B1Methods for partially saving a branch predictor stateAPPLE INC·Filed 2016·Granted Mar 5, 2019·10 cites·20 claims
- 0391US10203959B1Subroutine power optimiztionAPPLE INC·Filed 2016·Granted Feb 12, 2019·9 cites·17 claims
- 0487US11556485B1Processor with reduced interrupt latencyAPPLE INC·Filed 2021·Granted Jan 17, 2023·3 cites·20 claims
- 0585US8935485B2Snoop filter and non-inclusive shared cache memoryJALAL JAMSHED·Filed 2011·Granted Jan 13, 2015·10 cites·21 claims
- 0684US10007616B1Methods for core recovery after a cold startAPPLE INC·Filed 2016·Granted Jun 26, 2018·4 cites·20 claims
- 0783US8490107B2Processing resource allocation within an integrated circuit supporting transaction requests of different priority levelsJALAL JAMSHED·Filed 2011·Granted Jul 16, 2013·9 cites·22 claims
- 0880US8301932B2Synchronising between clock domainsHAY TIMOTHY NICHOLAS·Filed 2009·Granted Oct 30, 2012·16 cites·21 claims
- 0976US12242855B2Coprocessor operation bundlingAPPLE INC·Filed 2023·Granted Mar 4, 2025·0 cites·20 claims
- 1075US12487927B2Remote cache invalidationAPPLE INC·Filed 2024·Granted Dec 2, 2025·0 cites·18 claims
- 1174US8285912B2Communication infrastructure for a data processing apparatus and a method of operation of such a communication infrastructureFEERO BRETT STANLEY·Filed 2009·Granted Oct 9, 2012·9 cites·21 claims
- 1273US11210100B2Coprocessor operation bundlingAPPLE INC·Filed 2019·Granted Dec 28, 2021·1 cites·20 claims
- 1373US10776125B2Coprocessor memory ordering tableAPPLE INC·Filed 2018·Granted Sep 15, 2020·1 cites·20 claims
- 1473US10613867B1Suppressing pipeline redirection indicationsAPPLE INC·Filed 2017·Granted Apr 7, 2020·3 cites·16 claims
- 1573US9411362B2Storage circuitry and method for propagating data values across a clock boundaryADVANCED RISC MACH LTD·Filed 2014·Granted Aug 9, 2016·3 cites·16 claims
- 1673US8775754B2Memory controller and method of selecting a transaction using a plurality of ordered listsCAMPBELL MICHAEL ANDREW·Filed 2011·Granted Jul 8, 2014·5 cites·28 claims
- 1772US10922232B1Using cache memory as RAM with external access supportAPPLE INC·Filed 2019·Granted Feb 16, 2021·1 cites·20 claims
- 1868US11755328B2Coprocessor operation bundlingAPPLE INC·Filed 2021·Granted Sep 12, 2023·0 cites·20 claims
- 1962US9477600B2Apparatus and method for shared cache control including cache lines selectively operable in inclusive or non-inclusive modeJALAL JAMSHED·Filed 2011·Granted Oct 25, 2016·1 cites·24 claims
- 2059US11055102B2Coprocessor memory ordering tableAPPLE INC·Filed 2020·Granted Jul 6, 2021·0 cites·20 claims
- 2157US12001847B1Processor implementing parallel in-order execution during load missesAPPLE INC·Filed 2022·Granted Jun 4, 2024·0 cites·20 claims
- 2257US11093249B2Methods for partially preserving a branch predictor stateAPPLE INC·Filed 2019·Granted Aug 17, 2021·0 cites·20 claims
- 2354US11893413B2Virtual channel support using write tableAPPLE INC·Filed 2021·Granted Feb 6, 2024·0 cites·20 claims
- 2453US2025094355A1Translation Lookaside Buffer Entry LockingAPPLE INC·Filed 2023·Application pending·0 cites
- 2546US9880961B2Asynchronous bridge circuitry and a method of transferring data using asynchronous bridge circuitryADVANCED RISC MACH LTD·Filed 2013·Granted Jan 30, 2018·0 cites·17 claims
- 2645US10445091B1Ordering instructions in a processing core instruction bufferAPPLE INC·Filed 2016·Granted Oct 15, 2019·0 cites·20 claims
- 2741US2013042252A1Processing resource allocation within an integrated circuitADVANCED RISC MACH LTD·Filed 2011·Application pending·0 cites
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