Inventor · disambiguated record
Keerthinarayan P. Heragu
Also filed as: HERAGU KEERTHINARAYAN · HERAGU KEERTHINARAYAN P
11 granted patents·2 pending applications·26 citations·filing 2000–2015
84Inventor score
Top patents by PatentIndex Score
13 records- 0168US7573307B2Systems and methods for reduced area delay locked loopTEXAS INSTRUMENTS INC·Filed 2007·Granted Aug 11, 2009·8 cites·10 claims
- 0262US7719332B2Glitch reduced delay lock loop circuits and methods for using suchTEXAS INSTRUMENTS INC·Filed 2007·Granted May 18, 2010·6 cites·6 claims
- 0356US8301431B2Apparatus and method for accelerating simulations and designing integrated circuits and other systemsHERAGU KEERTHINARAYAN P·Filed 2008·Granted Oct 30, 2012·2 cites·20 claims
- 0447US6553547B1Method and system for generating charge sharing test vectorsTEXAS INSTRUMENTS INC·Filed 2000·Granted Apr 22, 2003·4 cites·9 claims
- 0544US6930953B2Self-timed strobe generator and method for use with multi-strobe random access memories to increase memory bandwidthTEXAS INSTRUMENTS INC·Filed 2003·Granted Aug 16, 2005·4 cites·19 claims
- 0641US7932756B2Master slave delay locked loops and uses thereofTEXAS INSTRUMENTS INC·Filed 2007·Granted Apr 26, 2011·1 cites·10 claims
- 0737US10146506B2Efficient implementation of a multiplier/accumulator with loadTEXAS INSTRUMENTS INC·Filed 2015·Granted Dec 4, 2018·0 cites·13 claims
- 0837US9672192B2High performance implementation of the FFT butterfly computationTEXAS INSTRUMENTS INC·Filed 2015·Granted Jun 6, 2017·0 cites·3 claims
- 0936US7216247B2Methods and systems to reduce data skew in FIFOsTEXAS INSTRUMENTS INC·Filed 2004·Granted May 8, 2007·1 cites·11 claims
- 1033US2009033386A1Delay Lock Loop Circuits Including Glitch Reduction and Methods for Using SuchTEXAS INSTRUMENTS INC·Filed 2007·Application pending·0 cites
- 1132US7550993B2Glitch reduced compensated circuits and methods for using suchTEXAS INSTRUMENTS INC·Filed 2007·Granted Jun 23, 2009·0 cites·19 claims
- 1228US8266464B2Power controller, a method of operating the power controller and a semiconductor memory system employing the sameCLINTON MICHAEL P·Filed 2007·Granted Sep 11, 2012·0 cites·14 claims
- 1328US2005144525A1Method to test memories that operate at twice their nominal bandwidthFiled 2003·Application pending·0 cites
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