Inventor

NOWAK EDWARD J

US591 patents

⚠️ This page may combine multiple inventors who share the name “NOWAK EDWARD J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NOWAK EDWARD J

IBM

Vertical field effect transistors

Low-cost high-performance planar back-gate CMOS

Substrate backgate for trigate FET

Multiple-gate device with floating back gate

Concurrent Fin-FET and thick-body device fabrication

FinFET transistor and circuit

Low capacitance junction-isolation for bulk FinFET technology

Four-bit FinFET NVRAM memory device

High-performance CMOS SOI devices on hybrid crystal-oriented substrates

Planar substrate devices integrated with finfets and method of manufacture

FinFET SRAM cell with chevron FinFET logic

Strained Fin FETs structure and method

Method for fabricating multiple-plane FinFET CMOS

High mobility crystalline planes in double-gate CMOS technology

FinFET layout generation

FinFET CMOS with NVRAM capability

Multiple-plane FinFET CMOS

Strained fin FETs structure and method

Method for forming asymmetric dual gate transistor

Variable threshold voltage double gated transistors and method of fabrication

Semiconductor diode with silicide films and trench isolation

Ultra dense vertical transport FET circuits

Semiconductor structures with pair(s) of vertical field effect transistors, each pair having a shared source/drain region and methods of forming the structures

Dense pitch bulk FinFET process by selective EPI and etch

Fin-type field effect transistor structure with merged source/drain silicide and method of forming the structure

Graphene-based transistor

Fin-type antifuse

Fin-type field effect transistor structure with merged source/drain silicide and method of forming the structure

Dynamic control of back gate bias in a FinFET SRAM cell

Field effect transistor with raised source/drain fin straps

Fin-type field effect transistor

Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETs

Double gated transistor and method of fabrication

FinFET with low gate capacitance and low extrinsic resistance

FinFET SRAM cell using low mobility plane for cell stability and method for forming

High mobility plane CMOS SOI

Finfet SRAM cell using low mobility plane for cell stability and method for forming

Multi-height FinFETS

High-density split-gate FinFET

Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same

Strained fin FETs structure and method

Fin FET devices from bulk semiconductor and method for forming

Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same

Methods for forming decoupling capacitors

Vertical trench-formed dual-gate FET device structure and method for creation

Method and apparatus for increasing interchip communications rates

Planarized silicon fin device

High reliability I/O stacked fets

GLOBALFOUNDRIES INC

Hybrid gate-all-around (GAA) field effect transistor (FET) structure and method of forming

Damascene wires with top via structures