Inventor · disambiguated record
Kaushik A. Kumar
Also filed as: KUMAR KAUSHIK · KUMAR KAUSHIK A · KUMAR KAUSHIK ARUN
54 granted patents·16 pending applications·492 citations·filing 2002–2021
98Inventor score
Top patents by PatentIndex Score
70 records- 0195US6975032B2Copper recess process with application to selective capping and electroless platingIBM·Filed 2002·Granted Dec 13, 2005·85 cites·19 claims
- 0292US7064064B2Copper recess process with application to selective capping and electroless platingIBM·Filed 2005·Granted Jun 20, 2006·22 cites·10 claims
- 0391US8551877B2Sidewall and chamfer protection during hard mask removal for interconnect patterningRANJAN ALOK·Filed 2012·Granted Oct 8, 2013·12 cites·20 claims
- 0490US7470616B1Damascene wiring fabrication methods incorporating dielectric cap etch process with hard mask retentionIBM·Filed 2008·Granted Dec 30, 2008·29 cites·1 claims
- 0590US7049209B1De-fluorination of wafer surface and related structureIBM·Filed 2005·Granted May 23, 2006·16 cites·18 claims
- 0689US7629264B2Structure and method for hybrid tungsten copper metal contactIBM·Filed 2008·Granted Dec 8, 2009·18 cites·19 claims
- 0789US7241681B2Bilayered metal hardmasks for use in dual damascene etch schemesIBM·Filed 2006·Granted Jul 10, 2007·13 cites·8 claims
- 0888US8592327B2Formation of SiOCl-containing layer on exposed low-k surfaces to reduce low-k damageRANJAN ALOK·Filed 2012·Granted Nov 26, 2013·9 cites·20 claims
- 0988US8367544B2Self-aligned patterned etch stop layers for semiconductor devicesIBM·Filed 2009·Granted Feb 5, 2013·16 cites·11 claims
- 1086US7659160B2Field effect transistors (FETS) with inverted source/drain metallic contacts, and method of fabrication sameIBM·Filed 2007·Granted Feb 9, 2010·12 cites·10 claims
- 1186US7224021B2MOSFET with high angle sidewall gate and contacts for reduced miller capacitanceIBM·Filed 2005·Granted May 29, 2007·9 cites·12 claims
- 1286US7057287B2Dual damascene integration of ultra low dielectric constant porous materialsIBM·Filed 2003·Granted Jun 6, 2006·34 cites·29 claims
- 1384US7358182B2Method of forming an interconnect structureIBM·Filed 2005·Granted Apr 15, 2008·11 cites·11 claims
- 1483US7338895B2Method for dual damascene integration of ultra low dielectric constant porous materialsIBM·Filed 2006·Granted Mar 4, 2008·9 cites·33 claims
- 1582US8945408B2Etch process for reducing directed self assembly pattern defectivityTOKYO ELECTRON LTD·Filed 2013·Granted Feb 3, 2015·6 cites·21 claims
- 1681US8809194B2Formation of SiOCl-containing layer on spacer sidewalls to prevent CD loss during spacer etchRANJAN ALOK·Filed 2012·Granted Aug 19, 2014·5 cites·19 claims
- 1781US7084479B2Line level air gapsIBM·Filed 2003·Granted Aug 1, 2006·27 cites·15 claims
- 1880US7122462B2Back end interconnect with a shaped interfaceINFINEON TECHNOLOGIES AG·Filed 2003·Granted Oct 17, 2006·25 cites·5 claims
- 1976US7833893B2Method for forming conductive structuresIBM·Filed 2007·Granted Nov 16, 2010·5 cites·20 claims
- 2076US7737561B2Dual damascene integration of ultra low dielectric constant porous materialsIBM·Filed 2008·Granted Jun 15, 2010·5 cites·25 claims
- 2176US7732288B2Method for fabricating a semiconductor structureIBM·Filed 2009·Granted Jun 8, 2010·4 cites·16 claims
- 2276US7648871B2Field effect transistors (FETS) with inverted source/drain metallic contacts, and method of fabricating sameIBM·Filed 2005·Granted Jan 19, 2010·6 cites·20 claims
- 2376US7052621B2Bilayered metal hardmasks for use in Dual Damascene etch schemesIBM·Filed 2003·Granted May 30, 2006·15 cites·15 claims
- 2475US8030157B1Liner protection in deep trench etchingIBM·Filed 2010·Granted Oct 4, 2011·4 cites·8 claims
- 2574US7888252B2Self-aligned contactIBM·Filed 2009·Granted Feb 15, 2011·4 cites·18 claims
- 2673US7396758B2Polycarbosilane buried etch stops in interconnect structuresIBM·Filed 2007·Granted Jul 8, 2008·4 cites·1 claims
- 2773US7241696B2Method for depositing a metal layer on a semiconductor interconnect structure having a capping layerINFINEON TECHNOLOGIES AG·Filed 2002·Granted Jul 10, 2007·20 cites·19 claims
- 2871US7253098B2Maintaining uniform CMP hard mask thicknessIBM·Filed 2004·Granted Aug 7, 2007·13 cites·7 claims
- 2969US8808562B2Dry metal etching methodOHSAWA YUSUKE·Filed 2011·Granted Aug 19, 2014·3 cites·15 claims
- 3068US9153457B2Etch process for reducing directed self assembly pattern defectivity using direct current positioningTOKYO ELECTRON LTD·Filed 2013·Granted Oct 6, 2015·2 cites·19 claims
- 3168US7825019B2Structures and methods for reduction of parasitic capacitances in semiconductor integrated circuitsIBM·Filed 2007·Granted Nov 2, 2010·4 cites·14 claims
- 3265US9653319B2Method for using post-processing methods for accelerating EUV lithographyTOKYO ELECTRON LTD·Filed 2014·Granted May 16, 2017·1 cites·15 claims
- 3365US6875688B1Method for reactive ion etch processing of a dual damascene structureIBM·Filed 2004·Granted Apr 5, 2005·12 cites·16 claims
- 3463US7659616B2On-chip cooling systems for integrated circuitsIBM·Filed 2007·Granted Feb 9, 2010·2 cites·15 claims
- 3562US7125792B2Dual damascene structure and methodIBM·Filed 2003·Granted Oct 24, 2006·8 cites·24 claims
- 3661US8058176B2Methods of patterning insulating layers using etching techniques that compensate for etch rate variationsPARK WAN-JAE·Filed 2007·Granted Nov 15, 2011·3 cites·4 claims
- 3761US7187081B2Polycarbosilane buried etch stops in interconnect structuresIBM·Filed 2003·Granted Mar 6, 2007·7 cites·16 claims
- 3860US7541277B1Stress relaxation, selective nitride phase removalIBM·Filed 2008·Granted Jun 2, 2009·2 cites·1 claims
- 3958US7718525B2Metal interconnect forming methods and IC chip including metal interconnectIBM·Filed 2007·Granted May 18, 2010·1 cites·15 claims
- 4058US7091612B2Dual damascene structure and methodIBM·Filed 2003·Granted Aug 15, 2006·8 cites·26 claims
- 4155US7879717B2Polycarbosilane buried etch stops in interconnect structuresIBM·Filed 2008·Granted Feb 1, 2011·0 cites·14 claims
- 4253US8664012B2Combined silicon oxide etch and contamination removal processGAYLORD RICHARD H·Filed 2011·Granted Mar 4, 2014·1 cites·19 claims
- 4352US2007184621A1Mosfet wth high angle sidewall gate and contacts for reduced miller capacitanceIBM·Filed 2007·Application pending·0 cites
- 4451US2008197495A1Structure for reducing lateral fringe capacitance in semiconductor devicesIBM·Filed 2008·Application pending·0 cites
- 4550US12438038B2Forming vias in a semiconductor deviceTOKYO ELECTRON LTD·Filed 2021·Granted Oct 7, 2025·0 cites·20 claims
- 4650US7696025B2Sidewall semiconductor transistorsIBM·Filed 2007·Granted Apr 13, 2010·0 cites·19 claims
- 4749US10079151B2Method for bottom-up deposition of a film in a recessed featureTOKYO ELECTRON LTD·Filed 2016·Granted Sep 18, 2018·0 cites·16 claims
- 4849US7494915B2Back end interconnect with a shaped interfaceIBM·Filed 2006·Granted Feb 24, 2009·0 cites·7 claims
- 4949US7456099B2Method of forming a structure for reducing lateral fringe capacitance in semiconductor devicesIBM·Filed 2006·Granted Nov 25, 2008·0 cites·8 claims
- 5048US2009283912A1Damascene wiring fabrication methods incorporating dielectric cap etch process with hard mask retentionAKINMADE-YUSUFF HAKEEM B S·Filed 2008·Application pending·0 cites
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