Inventor · disambiguated record
Steven Alan Lytle
Also filed as: LYTLE STEVEN A · LYTLE STEVEN ALAN
16 granted patents·1 pending application·312 citations·filing 1991–2018
94Inventor score
Files withTEXAS INSTRUMENTS INC5AGERE SYSTEMS INC4LUCENT TECHNOLOGIES INC3AGERE SYST GUARDIAN CORP2AT & T BELL LAB1
Top patents by PatentIndex Score
17 records- 0188US9245894B2Self aligned active trench contactTEXAS INSTRUMENTS INC·Filed 2014·Granted Jan 26, 2016·6 cites·12 claims
- 0284US6362638B1Stacked via Kelvin resistance test structure for measuring contact anomalies in multi-level metal integrated circuit technologiesAGERE SYST GUARDIAN CORP·Filed 1999·Granted Mar 26, 2002·61 cites·18 claims
- 0383US5100827ABuried antifuseAT & T BELL LAB·Filed 1991·Granted Mar 31, 1992·78 cites·5 claims
- 0481US9640539B2Self aligned active trench contactTEXAS INSTRUMENTS INC·Filed 2015·Granted May 2, 2017·2 cites·8 claims
- 0581US5891784ATransistor fabrication methodLUCENT TECHNOLOGIES INC·Filed 1995·Granted Apr 6, 1999·70 cites·6 claims
- 0680US8728945B2Method for patterning sublithographic featuresLYTLE STEVEN ALAN·Filed 2011·Granted May 20, 2014·7 cites·8 claims
- 0780US6879046B2Split barrier layer including nitrogen-containing portion and oxygen-containing portionAGERE SYSTEMS INC·Filed 2002·Granted Apr 12, 2005·22 cites·13 claims
- 0870US7250334B2Metal insulator metal (MIM) capacitor fabrication with sidewall spacers and aluminum cap (ALCAP) top electrodeTEXAS INSTRUMENTS INC·Filed 2004·Granted Jul 31, 2007·17 cites·20 claims
- 0966US6989602B1Dual damascene process with no passing metal featuresAGERE SYSTEMS INC·Filed 2000·Granted Jan 24, 2006·14 cites·2 claims
- 1062US10665596B2Self aligned active trench contactTEXAS INSTRUMENTS INC·Filed 2018·Granted May 26, 2020·0 cites·24 claims
- 1159US10134746B2Self aligned active trench contactTEXAS INSTRUMENTS INC·Filed 2017·Granted Nov 20, 2018·0 cites·15 claims
- 1253US6218085B1Process for photoresist rework to avoid sodium incorporationLUCENT TECHNOLOGIES INC·Filed 1999·Granted Apr 17, 2001·14 cites·20 claims
- 1350US7160799B2Define via in dual damascene processAGERE SYSTEMS INC·Filed 2003·Granted Jan 9, 2007·4 cites·14 claims
- 1448US6555910B1Use of small openings in large topography features to improve dielectric thickness control and a method of manufacture thereofAGERE SYSTEMS INC·Filed 2000·Granted Apr 29, 2003·2 cites·26 claims
- 1546US2009102501A1Test structures for e-beam testing of systematic and random defects in integrated circuitsGULDI RICHARD L·Filed 2007·Application pending·0 cites
- 1644US6329281B1Methods for fabricating a multilevel interconnection for an integrated circuit device utilizing a selective overlayerAGERE SYST GUARDIAN CORP·Filed 1999·Granted Dec 11, 2001·13 cites·21 claims
- 1726US5712176ADoping of silicon layersLUCENT TECHNOLOGIES INC·Filed 1995·Granted Jan 27, 1998·2 cites·10 claims
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