Inventor · disambiguated record
Boris A. Babayan
Also filed as: BABAYAN BORIS A · BABAYAN BORIS ARTASHESOVICH
12 granted patents·8 pending applications·20 citations·filing 2008–2016
85Inventor score
Technology areasG06F
Top patents by PatentIndex Score
20 records- 0182US10514927B2Instruction and logic for sorting and retiring storesINTEL CORP·Filed 2014·Granted Dec 24, 2019·11 cites·20 claims
- 0270US10133582B2Instruction and logic for identifying instructions for retirement in a multi-strand out-of-order processorINTEL CORP·Filed 2013·Granted Nov 20, 2018·3 cites·20 claims
- 0368US10095623B2Hardware apparatuses and methods to control access to a multiple bank data cacheINTEL CORP·Filed 2016·Granted Oct 9, 2018·1 cites·24 claims
- 0465US9645819B2Method and apparatus for reducing area and complexity of instruction wakeup logic in a multi-strand out-of-order processorIYER JAYESH·Filed 2012·Granted May 9, 2017·3 cites·30 claims
- 0563US9471501B2Hardware apparatuses and methods to control access to a multiple bank data cacheINTEL CORP·Filed 2014·Granted Oct 18, 2016·1 cites·24 claims
- 0653US9529596B2Method and apparatus for scheduling instructions in a multi-strand out of order processor with instruction synchronization bits and scoreboard bitsBABAYAN BORIS A·Filed 2011·Granted Dec 27, 2016·1 cites·12 claims
- 0750US10579378B2Instructions for manipulating a multi-bit predicate register for predicating instruction sequencesINTEL CORP·Filed 2014·Granted Mar 3, 2020·0 cites·24 claims
- 0848US2017235578A1Method and Apparatus for Scheduling of Instructions in a Multi-Strand Out-Of-Order ProcessorINTEL CORP·Filed 2016·Application pending·0 cites
- 0946US10235171B2Method and apparatus to efficiently handle allocation of memory ordering buffers in a multi-strand out-of-order loop processorINTEL CORP·Filed 2016·Granted Mar 19, 2019·0 cites·20 claims
- 1045US2016055004A1Method and apparatus for non-speculative fetch and execution of control-dependent blocksGROCHOWSKI EDWARD T·Filed 2014·Application pending·0 cites
- 1144US10241801B2Method and apparatus to create register windows for parallel iterations to achieve high performance in HW-SW codesigned loop acceleratorINTEL CORP·Filed 2016·Granted Mar 26, 2019·0 cites·22 claims
- 1244US2016306742A1Instruction and logic for memory access in a clustered wide-execution machineINTEL CORP·Filed 2013·Application pending·0 cites
- 1343US10241794B2Apparatus and methods to support counted loop exits in a multi-strand loop processorINTEL CORP·Filed 2016·Granted Mar 26, 2019·0 cites·20 claims
- 1443US10241789B2Method to do control speculation on loads in a high performance strand-based loop acceleratorINTEL CORP·Filed 2016·Granted Mar 26, 2019·0 cites·20 claims
- 1542US2016364237A1Processor logic and method for dispatching instructions from multiple strandsINTEL CORP·Filed 2014·Application pending·0 cites
- 1640US2011107314A1Static code recognition for binary translationBABAYAN BORIS ARTASHESOVICH·Filed 2008·Application pending·0 cites
- 1736US2018181398A1Apparatus and methods of decomposing loops to improve performance and power efficiencyINTEL CORP·Filed 2016·Application pending·0 cites
- 1835US2017090929A1Hardware-assisted software verification and secure executionMCAFEE INC·Filed 2015·Application pending·0 cites
- 1933US2014208074A1Instruction scheduling for a multi-strand out-of-order processorBABAYAN BORIS A·Filed 2012·Application pending·0 cites
- 2032US9811340B2Method and apparatus for reconstructing real program order of instructions in multi-strand out-of-order processorKOSAREV NIKOLAY·Filed 2012·Granted Nov 7, 2017·0 cites·21 claims
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