Inventor · disambiguated record
Mahesh A. Iyer
Also filed as: IYER MAHESH · IYER MAHESH A · IYER MAHESH ANANTHARAMAN
93 granted patents·17 pending applications·543 citations·filing 1994–2025
99Inventor score
Top patents by PatentIndex Score
110 records- 0194US10333535B1Techniques for signal skew compensationALTERA CORP·Filed 2016·Granted Jun 25, 2019·11 cites·15 claims
- 0294US10101387B1Sharing a JTAG interface among multiple partitionsINTEL CORP·Filed 2017·Granted Oct 16, 2018·18 cites·20 claims
- 0394US9922157B1Sector-based clock routing methods and apparatusALTERA CORP·Filed 2015·Granted Mar 20, 2018·14 cites·27 claims
- 0491US10235485B1Partial reconfiguration debugging using hybrid modelsALTERA CORP·Filed 2016·Granted Mar 19, 2019·10 cites·10 claims
- 0591US7302417B2Method and apparatus for improving efficiency of constraint solvingSYNOPSYS INC·Filed 2005·Granted Nov 27, 2007·25 cites·9 claims
- 0690US10162918B1Integrated circuit retiming with selective modeling of flip-flop secondary signalsALTERA CORP·Filed 2016·Granted Dec 25, 2018·9 cites·17 claims
- 0790US7937682B2Method and apparatus for automatic orientation optimizationSYNOPSYS INC·Filed 2008·Granted May 3, 2011·26 cites·33 claims
- 0890US7853915B2Interconnect-driven physical synthesis using persistent virtual routingSYNOPSYS INC·Filed 2008·Granted Dec 14, 2010·31 cites·51 claims
- 0989US10169518B1Methods for delaying register reset for retimed circuitsINTEL CORP·Filed 2016·Granted Jan 1, 2019·6 cites·19 claims
- 1089US9824177B1Method and apparatus for verifying structural correctness in retimed circuitsALTERA CORP·Filed 2016·Granted Nov 21, 2017·5 cites·19 claims
- 1188US11101804B2Fast memory for programmable devicesINTEL CORP·Filed 2019·Granted Aug 24, 2021·4 cites·20 claims
- 1288US10339241B1Methods for incremental circuit design legalization during physical synthesisALTERA CORP·Filed 2016·Granted Jul 2, 2019·6 cites·13 claims
- 1387US10417374B1Method and apparatus for performing register retiming by utilizing native timing-driven constraintsALTERA CORP·Filed 2016·Granted Sep 17, 2019·5 cites·19 claims
- 1487US10157247B2Method and apparatus for performing rewind structural verification of retimed circuits driven by a plurality of clocksINTEL CORP·Filed 2017·Granted Dec 18, 2018·5 cites·20 claims
- 1585US11609262B2On-die aging measurements for dynamic timing modelingINTEL CORP·Filed 2018·Granted Mar 21, 2023·2 cites·20 claims
- 1683US10936772B1Methods for incremental circuit physical synthesisALTERA CORP·Filed 2016·Granted Mar 2, 2021·4 cites·20 claims
- 1783US6789232B1Construction of a technology library for use in an electronic design automation system that converts the technology library into non-linear, gain-based models for estimating circuit delaySYNOPSYS INC·Filed 2002·Granted Sep 7, 2004·35 cites·20 claims
- 1881US11574101B2Techniques for providing optimizations based on categories of slack in timing pathsINTEL CORP·Filed 2021·Granted Feb 7, 2023·2 cites·20 claims
- 1980US7512912B1Method and apparatus for solving constraints for word-level networksSYNOPSYS INC·Filed 2003·Granted Mar 31, 2009·18 cites·19 claims
- 2079US8316339B2Zone-based leakage power optimizationIYER MAHESH A·Filed 2010·Granted Nov 20, 2012·7 cites·21 claims
- 2179US8266570B2Density-based area recovery in electronic design automationWALKER ROBERT·Filed 2010·Granted Sep 11, 2012·5 cites·21 claims
- 2279US2025286555A1Power Management using Voltage Islands on Programmable Logic DevicesALTERA CORP·Filed 2025·Application pending·0 cites
- 2378US12216150B2On-die aging measurements for dynamic timing modelingINTEL CORP·Filed 2022·Granted Feb 4, 2025·0 cites·20 claims
- 2478US6912702B1Non-linear, gain-based modeling of circuit delay for an electronic design automation systemSYNOPSYS INC·Filed 2002·Granted Jun 28, 2005·20 cites·24 claims
- 2577US8826218B2Accurate approximation of the objective function for solving the gate-sizing problem using a numerical solverSYNOPSYS INC·Filed 2013·Granted Sep 2, 2014·4 cites·15 claims
- 2677US2025271826A1Systems and methods to reduce voltage guardbandALTERA CORP·Filed 2025·Application pending·0 cites
- 2776US8799843B1Identifying candidate nets for buffering using numerical methodsSYNOPSYS INC·Filed 2013·Granted Aug 5, 2014·4 cites·15 claims
- 2876US8707242B2Optimizing a circuit design for delay using load-and-slew-independent numerical delay modelsMOTTAEZ AMIR H·Filed 2012·Granted Apr 22, 2014·4 cites·20 claims
- 2975US12379698B2Systems and methods to reduce voltage guardbandINTEL CORP·Filed 2021·Granted Aug 5, 2025·0 cites·21 claims
- 3075US10965536B2Methods and apparatus to insert buffers in a dataflow graphINTEL CORP·Filed 2019·Granted Mar 30, 2021·2 cites·44 claims
- 3175US10303202B1Method and apparatus for performing clock allocation for a system implemented on a programmable deviceALTERA CORP·Filed 2016·Granted May 28, 2019·2 cites·22 claims
- 3275US9064073B2Hyper-concurrent optimization over multi-corner multi-mode scenariosMOTTAEZ AMIR H·Filed 2010·Granted Jun 23, 2015·4 cites·26 claims
- 3374US10162924B1Method and apparatus for performing large scale consensus based clusteringALTERA CORP·Filed 2016·Granted Dec 25, 2018·2 cites·19 claims
- 3474US9454626B2Solving an optimization problem using a constraints solverSYNOPSYS INC·Filed 2013·Granted Sep 27, 2016·3 cites·18 claims
- 3573US10242144B1Methods for minimizing logic overlap on integrated circuitsALTERA CORP·Filed 2016·Granted Mar 26, 2019·2 cites·13 claims
- 3673US8589846B2Modeling transition effects for circuit optimizationSYNOPSYS INC·Filed 2012·Granted Nov 19, 2013·2 cites·18 claims
- 3772US11113442B2Methods and apparatus for reducing reliability degradation on an integrated circuitINTEL CORP·Filed 2017·Granted Sep 7, 2021·1 cites·19 claims
- 3872US8527927B2Zone-based area recovery in electronic design automationWALKER ROBERT·Filed 2010·Granted Sep 3, 2013·3 cites·21 claims
- 3971US9280625B2Incremental slack margin propagationSYNOPSYS INC·Filed 2015·Granted Mar 8, 2016·1 cites·9 claims
- 4071US8621408B2Progressive circuit evaluation for circuit optimizationIYER MAHESH A·Filed 2012·Granted Dec 31, 2013·3 cites·18 claims
- 4170US10372850B2Methods for verifying retimed circuits with delayed initializationINTEL CORP·Filed 2016·Granted Aug 6, 2019·1 cites·23 claims
- 4270US10318686B2Methods for reducing delay on integrated circuits by identifying candidate placement locations in a leveled graphINTEL CORP·Filed 2016·Granted Jun 11, 2019·2 cites·15 claims
- 4370US8966430B1Robust numerical optimization for optimizing delay, area, and leakage powerSYNOPSYS INC·Filed 2013·Granted Feb 24, 2015·2 cites·15 claims
- 4470US7243087B2Method and apparatus for solving bit-slice operatorsSYNOPSYS INC·Filed 2003·Granted Jul 10, 2007·11 cites·8 claims
- 4569US12487658B2Workload-dependent integrated circuit operation based on power headroomINTEL CORP·Filed 2021·Granted Dec 2, 2025·0 cites·20 claims
- 4669US12355359B2Switch based on load currentINTEL CORP·Filed 2021·Granted Jul 8, 2025·0 cites·20 claims
- 4769US10354038B1Methods for bounding the number of delayed reset clock cycles for retimed circuitsINTEL CORP·Filed 2016·Granted Jul 16, 2019·1 cites·19 claims
- 4869US8826217B2Modeling gate size range by using a penalty function in a numerical gate sizing frameworkSYNOPSYS INC·Filed 2013·Granted Sep 2, 2014·2 cites·12 claims
- 4969US6334205B1Wavefront technology mappingIBM·Filed 1999·Granted Dec 25, 2001·56 cites·11 claims
- 5068US12429900B2Controlled transition between configuration mode and user mode to reduce current-resistance voltage dropINTEL CORP·Filed 2021·Granted Sep 30, 2025·0 cites·20 claims
Showing the top 50 of 110 patent records by PatentIndex Score.
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